alexforencich / verilog-mersenne
Verilog implementation of Mersenne Twister PRNG
☆27Updated 6 years ago
Alternatives and similar repositories for verilog-mersenne:
Users that are interested in verilog-mersenne are comparing it to the libraries listed below
- A simple DDR3 memory controller☆54Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 2 months ago
- Repository gathering basic modules for CDC purpose☆52Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- Verilog Content Addressable Memory Module☆102Updated 3 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 3 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated last month
- Verilog RTL Design☆32Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- ☆53Updated 4 years ago
- ☆26Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆100Updated 3 years ago
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- ☆29Updated 5 years ago
- Extensible FPGA control platform☆57Updated last year
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 7 months ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- openHMC - an open source Hybrid Memory Cube Controller☆46Updated 8 years ago
- ☆24Updated 3 years ago
- Platform Level Interrupt Controller☆36Updated 9 months ago