KULeuven-COSIC / COSO-TRNG
Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
☆12Updated this week
Related projects ⓘ
Alternatives and complementary repositories for COSO-TRNG
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- True Random Number Generator core implemented in Verilog.☆72Updated 4 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 3 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 7 years ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆10Updated 4 years ago
- Defense/Attack PUF Library (DA PUF Library)☆46Updated 4 years ago
- SHA3 (KECCAK)☆15Updated 10 years ago
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆43Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆43Updated this week
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆25Updated 2 years ago
- FPGA implementation of a physical unclonable function for authentication☆32Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated last month
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆37Updated 7 years ago
- Yet Another RISC-V Implementation☆85Updated 2 months ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- A demo system for Ibex including debug support and some peripherals☆55Updated 3 months ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆29Updated 4 months ago
- XCrypto: a cryptographic ISE for RISC-V☆92Updated last year
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago
- A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.☆9Updated 4 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 2 weeks ago
- ☆45Updated 3 years ago
- Verilog implementation of the SHA-512 hash function.☆37Updated 3 years ago
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆14Updated 3 years ago