KULeuven-COSIC / COSO-TRNGLinks
Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
☆13Updated last year
Alternatives and similar repositories for COSO-TRNG
Users that are interested in COSO-TRNG are comparing it to the libraries listed below
Sorting:
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 8 years ago
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆38Updated 3 years ago
- David Canright's tiny AES S-boxes☆28Updated 11 years ago
- AES hardware engine for Xilinx Zynq platform☆32Updated 4 years ago
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆72Updated 3 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆402Updated this week
- ☆59Updated 4 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆41Updated 2 weeks ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆12Updated 6 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆136Updated 3 years ago
- Parametric NTT/INTT Hardware Generator☆78Updated 4 years ago
- This repository is for our paper "High-Performance and Configurable SW/HW Co-design of Post-Quantum Signature CRYSTALS-Dilithium" in ACM …☆17Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- SHA3 (KECCAK)☆18Updated 11 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆55Updated 8 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Elgamal's over Elliptic Curves☆19Updated 7 years ago
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆18Updated 3 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆41Updated 8 years ago
- ☆25Updated 4 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 4 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆24Updated 3 years ago
- HW Design Collateral for Caliptra RoT IP☆124Updated last week
- Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions☆16Updated 3 months ago
- Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.☆17Updated 5 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆70Updated 8 years ago
- ☆25Updated 3 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year