Alternatives and similar repositories for COSO-TRNG

Users that are interested in COSO-TRNG are comparing it to the libraries listed below

• acmert / kyber-polmul-hw
  Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
  ☆37Updated 3 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• xingyf14 / CRYSTALS-Kyber
  ☆58Updated 4 years ago
• secworks / aes
  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…
  ☆371Updated 3 months ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆58Updated 2 years ago
• CityUHK-CALAS / SW-HW-Co-design-of-Dilithium
  This repository is for our paper "High-Performance and Configurable SW/HW Co-design of Post-Quantum Signature CRYSTALS-Dilithium" in ACM …
  ☆10Updated last year
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆31Updated 3 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆39Updated 8 years ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆82Updated 3 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• acmert / parametric-ntt
  Parametric NTT/INTT Hardware Generator
  ☆72Updated 4 years ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆134Updated 2 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆39Updated 5 years ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated last month
• coruus / canright-aes-sboxes
  David Canright's tiny AES S-boxes
  ☆24Updated 10 years ago
• pq-crypto / vpqc
  processor for post-quantum cryptography
  ☆16Updated 5 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆100Updated this week
• soc-hub-fi / Marian
  Modified version of PULP Ara to support Vector Cryptography (Zvk) Instructions
  ☆14Updated 9 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• stnolting / neoTRNG
  🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
  ☆193Updated 2 weeks ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆23Updated 7 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 3 years ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆32Updated this week
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆34Updated 10 years ago
• flokrieger / Aloha-HE
  ☆25Updated last month
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆172Updated last year