crypt-xie / XCryptCoreLinks
Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
☆38Updated 5 years ago
Alternatives and similar repositories for XCryptCore
Users that are interested in XCryptCore are comparing it to the libraries listed below
Sorting:
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆39Updated 8 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆53Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- Implementation of the PCIe physical layer☆42Updated last month
- Asynchronous fifo in verilog☆35Updated 9 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆56Updated last year
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- round robin arbiter☆74Updated 10 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆75Updated 7 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- AXI4 BFM in Verilog☆32Updated 8 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Generic AXI to APB bridge☆12Updated 10 years ago
- ☆36Updated 9 years ago
- AXI Interconnect☆49Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 4 months ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆74Updated 6 years ago
- opensource crypto IP core☆27Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago