Alternatives and similar repositories for sha512

Users that are interested in sha512 are comparing it to the libraries listed below

• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆37Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆57Updated 4 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• RoaLogic / apb4_gpio
  General Purpose IO with APB4 interface
  ☆12Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆41Updated 2 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆18Updated 5 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 7 months ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆44Updated 10 years ago
• raya4213 / VerilogCodeECC
  Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field
  ☆22Updated 8 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 10 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆57Updated 3 months ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆18Updated 3 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• HeerAmbavi / RSAonVerilog
  Implementation of RSA algorithm on FPGA using Verilog
  ☆28Updated 6 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆81Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆55Updated 4 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆23Updated 7 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆38Updated 3 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago