secworks / sha512Links
Verilog implementation of the SHA-512 hash function.
☆44Updated last week
Alternatives and similar repositories for sha512
Users that are interested in sha512 are comparing it to the libraries listed below
Sorting:
- True Random Number Generator core implemented in Verilog.☆79Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆32Updated 7 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- Yet Another RISC-V Implementation☆99Updated last year
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆23Updated 7 years ago
- DDR4 Simulation Project in System Verilog☆43Updated 11 years ago
- ☆28Updated 4 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 8 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆53Updated 10 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆24Updated last month
- A simple DDR3 memory controller☆61Updated 3 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Implementation of the SHA256 Algorithm in Verilog☆38Updated 14 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- USB -> AXI Debug Bridge☆42Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆24Updated 8 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated 3 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- Simple hash table on Verilog (SystemVerilog)☆51Updated 9 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year