adnanbaysal / TRNG-with-Ring-Oscillators-in-VerilogLinks
A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
☆11Updated 5 years ago
Alternatives and similar repositories for TRNG-with-Ring-Oscillators-in-Verilog
Users that are interested in TRNG-with-Ring-Oscillators-in-Verilog are comparing it to the libraries listed below
Sorting:
- AES hardware engine for Xilinx Zynq platform☆32Updated 4 years ago
- AES加密解密算法的Verilog实现☆67Updated 9 years ago
- SPI Slave for FPGA in Verilog and VHDL☆218Updated last year
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- ☆80Updated 3 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆76Updated last year
- Verilog UART☆187Updated 12 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆98Updated last year
- 国产VU13P加速卡资料☆80Updated 9 months ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆401Updated 8 months ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆159Updated 9 months ago
- ☆144Updated 5 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Updated last week
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆146Updated 2 years ago
- SPI Master for FPGA - VHDL and Verilog☆316Updated 2 years ago
- Example designs for FPGA Drive FMC☆281Updated 11 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆74Updated 5 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago
- Verilog digital signal processing components☆161Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- PCI express simulation framework for Cocotb☆185Updated 3 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Verilog based BCH encoder/decoder☆129Updated 3 years ago
- IEEE P1735 decryptor for VHDL☆38Updated 10 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 7 years ago
- True Random Number Generator core implemented in Verilog.☆78Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- I2C Master and Slave☆38Updated 10 years ago