KULeuven-COSIC / NTRU_NTT_HWLinks
☆25Updated 4 years ago
Alternatives and similar repositories for NTRU_NTT_HW
Users that are interested in NTRU_NTT_HW are comparing it to the libraries listed below
Sorting:
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆19Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆15Updated 2 months ago
- ☆26Updated 2 years ago
- ☆24Updated last year
- ☆27Updated 3 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 4 years ago
- Parametric NTT/INTT Hardware Generator☆80Updated 4 years ago
- ☆28Updated 5 months ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆18Updated 4 years ago
- ☆36Updated last year
- Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)☆65Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆23Updated 5 years ago
- SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…☆25Updated 2 months ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆43Updated this week
- processor for post-quantum cryptography☆17Updated 5 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆37Updated 11 years ago
- Defense/Attack PUF Library (DA PUF Library)☆55Updated 5 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- A Hardware Implemented Poseidon Hasher☆19Updated 3 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆14Updated last year
- Griffinfly is COSIC's submission to the ZPRIZE competition under the category, Accelerating NTT Operations on an FPGA by Michiel Van Beir…☆11Updated 2 years ago
- FPGA implementation of a physical unclonable function for authentication☆33Updated 8 years ago
- ☆13Updated 10 years ago
- Alveo Versal Example Design☆55Updated last month
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆36Updated this week
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆52Updated 7 years ago
- Memory Compiler Tutorial☆13Updated 3 years ago
- ☆26Updated 5 years ago
- This script generates and analyzes prefix tree adders.☆39Updated 4 years ago