KULeuven-COSIC / NTRU_NTT_HWLinks
☆23Updated 4 years ago
Alternatives and similar repositories for NTRU_NTT_HW
Users that are interested in NTRU_NTT_HW are comparing it to the libraries listed below
Sorting:
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆18Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆33Updated last year
- ☆20Updated last year
- ☆26Updated 2 years ago
- Parametric NTT/INTT Hardware Generator☆72Updated 4 years ago
- ☆26Updated last month
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆17Updated 4 years ago
- Repo for code developed during the HEAT project (Homomorphic Encryption Applications Technology)☆61Updated 5 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆34Updated 10 years ago
- ☆35Updated last year
- ☆23Updated 3 years ago
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 3 years ago
- Defense/Attack PUF Library (DA PUF Library)☆51Updated 5 years ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆50Updated 7 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆34Updated this week
- ☆26Updated 4 years ago
- processor for post-quantum cryptography☆16Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆22Updated 4 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 5 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆37Updated 3 years ago
- Griffinfly is COSIC's submission to the ZPRIZE competition under the category, Accelerating NTT Operations on an FPGA by Michiel Van Beir…☆11Updated 2 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- Verilog RTL Implementation of DNN☆10Updated 7 years ago
- ☆39Updated last year
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- ☆13Updated 10 years ago
- Alveo Versal Example Design☆46Updated last month