airhdl / spi-to-axi-bridgeLinks
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
☆50Updated last year
Alternatives and similar repositories for spi-to-axi-bridge
Users that are interested in spi-to-axi-bridge are comparing it to the libraries listed below
Sorting:
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆39Updated last week
- UART models for cocotb☆30Updated 3 weeks ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆74Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆78Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- AXI Stream UART (verilog)☆11Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆46Updated 9 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- ☆33Updated 2 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year
- Slides and lab instructions for the mastering MicroBlaze session☆36Updated 3 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 2 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Ethernet interface modules for Cocotb☆70Updated 3 weeks ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆39Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆111Updated 4 years ago
- ☆15Updated 9 months ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆65Updated 4 months ago