airhdl / spi-to-axi-bridgeLinks
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
☆49Updated last year
Alternatives and similar repositories for spi-to-axi-bridge
Users that are interested in spi-to-axi-bridge are comparing it to the libraries listed below
Sorting:
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- UART -> AXI Bridge☆61Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- Python Tool for UVM Testbench Generation☆52Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- UART models for cocotb☆29Updated 2 years ago
- ☆21Updated last month
- ☆26Updated last year
- ☆41Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆37Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆68Updated this week
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated 2 weeks ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- ☆13Updated 5 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆43Updated 4 months ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 10 months ago
- ☆32Updated 2 years ago
- I2C models for cocotb☆35Updated 2 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated 5 months ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- ☆70Updated 3 years ago
- AXI Stream UART (verilog)☆11Updated 5 years ago