Alternatives and similar repositories for spi-to-axi-bridge:

Users that are interested in spi-to-axi-bridge are comparing it to the libraries listed below

• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆33Updated 10 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 2 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆50Updated 9 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆30Updated 11 months ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆65Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆52Updated 4 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 7 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆62Updated 5 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆19Updated 4 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆62Updated 4 years ago
• mbuesch / crcgen
  Generator for CRC HDL code (VHDL, Verilog, MyHDL)
  ☆33Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated this week
• hypernyan / eth_vlg
  ☆60Updated 3 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 8 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆101Updated 3 years ago
• amiq-consulting / physical_coding_library
  ☆18Updated 8 years ago
• suoto / fpga_cores
  ☆33Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 10 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 3 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago