Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
☆85Mar 28, 2026Updated 5 months ago
Alternatives and similar repositories for PeakRDL-regblock
Users that are interested in PeakRDL-regblock are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Control and status register code generator toolchain☆211Sep 1, 2026Updated 3 weeks ago
- Generate address space documentation HTML from compiled SystemRDL input☆65Updated this week
- ☆16Mar 28, 2026Updated 5 months ago
- Import and export IP-XACT XML register models☆39Nov 5, 2025Updated 10 months ago
- SystemRDL 2.0 language compiler front-end☆285Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Generate UVM register model from compiled SystemRDL input☆61Nov 25, 2025Updated 9 months ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 2 months ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆16Aug 28, 2026Updated 3 weeks ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated 3 months ago
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last week
- Tools based upon slang for language server purpose☆24Sep 10, 2026Updated last week
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 7 months ago
- Unified Coverage Interoperability Standard (UCIS)☆15Sep 2, 2026Updated 3 weeks ago
- IP-XACT XML binding library☆17Jun 23, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,941Updated this week
- SystemVerilog Logger☆19Apr 6, 2026Updated 5 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Jun 25, 2026Updated 2 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆23Sep 8, 2026Updated 2 weeks ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- ☆26Aug 10, 2023Updated 3 years ago
- SystemVerilog compiler and language services☆1,147Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,705Sep 17, 2026Updated last week
- An abstraction library for interfacing EDA tools☆796Sep 15, 2026Updated last week
- A SystemVerilog source file pickler.☆62Oct 20, 2024Updated last year
- VUnit is a unit testing framework for VHDL/SystemVerilog☆844Updated this week
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 3 months ago
- cocotb: Python-based chip (RTL) verification☆2,516Updated this week
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆24Sep 10, 2026Updated 2 weeks ago
- A flexible and scalable development platform for modern FPGA projects.☆47Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog plugin for Sublime Text☆51Mar 28, 2026Updated 5 months ago
- verilator testbench w/ Javascript using N-API☆18Feb 19, 2026Updated 7 months ago
- SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)☆11Jun 19, 2024Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆148Sep 17, 2026Updated last week
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆219Updated this week
- A VHDL implementation of an AXI4 Master☆16Nov 7, 2017Updated 8 years ago