A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.
☆14Nov 23, 2022Updated 3 years ago
Alternatives and similar repositories for fp8_mul
Users that are interested in fp8_mul are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Dec 15, 2023Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆124Apr 3, 2026Updated 3 months ago
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- ☆20Sep 28, 2024Updated last year
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆44Jan 15, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- git clone of http://code.google.com/p/axi-bfm/☆18May 21, 2013Updated 13 years ago
- bfloat16 dtype for numpy☆20Sep 25, 2023Updated 2 years ago
- ☆14Sep 27, 2021Updated 4 years ago
- ZC RISCV CORE☆12Dec 19, 2019Updated 6 years ago
- A curated directory of Svelte libraries.☆15Dec 1, 2025Updated 7 months ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆21Jul 10, 2026Updated last week
- Example for running IREE in a bare-metal Arm environment.☆43Feb 24, 2026Updated 4 months ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- Unit Scaling demo and experimentation code☆16Mar 12, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Benchmark tests supporting the TiledCUDA library.☆19Nov 19, 2024Updated last year
- Code for the Supabase & Prisma Tutorial Video☆12Feb 21, 2023Updated 3 years ago
- Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.☆69Oct 19, 2025Updated 9 months ago
- Dateset for MobiAct/MobiFall☆21May 5, 2023Updated 3 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 12 years ago
- ☆12Nov 27, 2022Updated 3 years ago
- Token ring communication protocol for low-cost, low-power embedded devices communicating over UART☆15May 3, 2018Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆55Dec 6, 2023Updated 2 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21May 12, 2025Updated last year
- A cheap but powerful CH55x BadUSB Cable with SL2.1s USBHUB, which makes the cable usable while executing payload. 廉价但强大，把CH552e和SL2.1s集成在…☆20Nov 23, 2022Updated 3 years ago
- Tiny Tapeout 06☆16Nov 15, 2025Updated 8 months ago
- ☆12Dec 19, 2022Updated 3 years ago
- ☆47Aug 23, 2023Updated 2 years ago
- A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated☆19Jan 27, 2019Updated 7 years ago
- Shell in slack :D☆14Mar 18, 2016Updated 10 years ago
- ☆12Sep 25, 2024Updated last year
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Notepad++ Jade syntax highlighter☆15Jun 25, 2016Updated 10 years ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 5 months ago
- ☆19Jul 25, 2018Updated 7 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆22Dec 10, 2018Updated 7 years ago
- An almost empty chisel project as a starting point for hardware design☆37Jan 27, 2025Updated last year
- ☆16Apr 10, 2024Updated 2 years ago