cchan / fp8_mulLinks
A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.
☆14Updated 3 years ago
Alternatives and similar repositories for fp8_mul
Users that are interested in fp8_mul are comparing it to the libraries listed below
Sorting:
- Synthesisable SIMT-style RISC-V GPGPU☆44Updated 4 months ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 11 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- ☆88Updated this week
- Wrappers for open source FPU hardware implementations.☆35Updated this week
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated 2 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last month
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 3 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- RISC-V GPGPU☆35Updated 5 years ago
- ☆35Updated last week
- Pulp virtual platform☆24Updated 4 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- Example for running IREE in a bare-metal Arm environment.☆39Updated 4 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 3 years ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆43Updated 10 months ago
- ☆14Updated 5 months ago
- ☆26Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆20Updated 6 months ago
- ☆12Updated 3 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 5 years ago
- Various examples for Chisel HDL☆29Updated 3 years ago