cchan / fp8_mul
A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.
☆14Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for fp8_mul
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆9Updated 10 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated last month
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆19Updated this week
- ☆21Updated last month
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- Wraps the NVDLA project for Chipyard integration☆19Updated 8 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated last year
- Verilog behavioral description of various memories☆30Updated 2 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆14Updated last month
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆25Updated 10 months ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- FPGA acceleration of arbitrary precision floating point computations.☆37Updated 2 years ago
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆17Updated 8 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆19Updated 3 months ago
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆13Updated 2 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆17Updated 7 months ago
- ☆36Updated last week
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆15Updated 3 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆49Updated 4 years ago
- ☆12Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated last month
- Library of open source Process Design Kits (PDKs)☆28Updated last week