cchan / fp8_mulLinks
A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.
☆14Updated 2 years ago
Alternatives and similar repositories for fp8_mul
Users that are interested in fp8_mul are comparing it to the libraries listed below
Sorting:
- ☆33Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆43Updated 4 months ago
- Various examples for Chisel HDL☆29Updated 3 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 11 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated 2 weeks ago
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- ☆84Updated this week
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- ☆32Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 3 weeks ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆21Updated 2 months ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- Pulp virtual platform☆24Updated 3 months ago
- ☆14Updated 4 months ago
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- Example for running IREE in a bare-metal Arm environment.☆39Updated 3 months ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Updated 4 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆20Updated 5 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆23Updated 4 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- ☆20Updated last year
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago