Digilent / axi4lite_ip_genLinks
Generates simple AXI4-lite IP for use in Vivado from register specifications
☆15Updated 9 months ago
Alternatives and similar repositories for axi4lite_ip_gen
Users that are interested in axi4lite_ip_gen are comparing it to the libraries listed below
Sorting:
- A collection of Opal Kelly provided design resources☆17Updated 2 months ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 11 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Many peripherals in Verilog ready to use☆41Updated last year
- Open FPGA Modules☆24Updated last year
- Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.☆30Updated 4 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆69Updated 2 months ago
- I2C Master Verilog module☆36Updated 8 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆75Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- ☆19Updated 2 years ago
- ☆117Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- JESD204b modules in VHDL☆30Updated 6 years ago
- Single Port RAM, Dual Port RAM, FIFO☆30Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- A collection of phase locked loop (PLL) related projects☆116Updated 2 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆41Updated 6 years ago
- IP Catalog for Raptor.☆17Updated last year
- VHDL PCIe Transceiver☆32Updated 5 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- A series of CORDIC related projects☆121Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 4 months ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆34Updated last year
- development interface mil-std-1553b for system on chip☆24Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- UART to AXI Stream interface written in VHDL☆18Updated 3 years ago