pulp-platform / axi_spi_slave
☆23Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for axi_spi_slave
- UART -> AXI Bridge☆58Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- ☆48Updated 3 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- A simple DDR3 memory controller☆51Updated last year
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆43Updated 11 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆69Updated 6 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- ☆20Updated 5 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- ☆26Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated 3 weeks ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- Implementation of the PCIe physical layer☆30Updated last week
- round robin arbiter☆68Updated 10 years ago
- IP operations in verilog (simulation and implementation on ice40)☆52Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- WISHBONE Interconnect☆11Updated 7 years ago