chipsalliance/verible-linter-action external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

chipsalliance/verible-linter-action

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/chipsalliance/verible-linter-action)

Close

chipsalliance / verible-linter-actionView on GitHubMore

• External links
• Readme badge

Automatic SystemVerilog linting in github actions with the help of Verible

☆37Oct 23, 2024Updated last year

Alternatives and similar repositories for verible-linter-action

Users that are interested in verible-linter-action are comparing it to the libraries listed below

• DreamCloud-Project / McSim-TLM-NoC

  View on GitHub
  Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level
  ☆10Aug 30, 2016Updated 9 years ago
• harshilasu / Intel-4004-CPU-in-Verilog

  View on GitHub
  Arizona State University CSE320
  ☆12Mar 22, 2015Updated 10 years ago
• verilator / verilator_ext_tests

  View on GitHub
  Extended and external tests for Verilator testing
  ☆17Feb 26, 2026Updated last week
• ezchi / uvm-systemc

  View on GitHub
  My local copy of UVM-SystemC
  ☆14Apr 27, 2024Updated last year
• chipsalliance / Cores-SweRV-Support-Package

  View on GitHub
  Processor support packages
  ☆19Feb 2, 2021Updated 5 years ago
• starfive-tech / opensbi

  View on GitHub
  ☆19Oct 13, 2025Updated 4 months ago
• levibyte / channel_router

  View on GitHub
  demo on simple channel router
  ☆13Jan 3, 2019Updated 7 years ago
• waviousllc / wav-lpddr-sw

  View on GitHub
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆23Feb 16, 2022Updated 4 years ago
• pulp-platform / cheshire-ihp130-o

  View on GitHub
  ☆59Mar 31, 2025Updated 11 months ago
• EECS150 / asic_labs_fa21

  View on GitHub
  ☆24Dec 8, 2021Updated 4 years ago
• PacoReinaCampo / MPSoC-NoC

  View on GitHub
  Network on Chip for MPSoC
  ☆28Feb 28, 2026Updated last week
• chipsalliance / uvm-verilator

  View on GitHub
  ☆119Nov 11, 2025Updated 3 months ago
• pulp-platform / bender

  View on GitHub
  A dependency management tool for hardware projects.
  ☆349Updated this week
• google / globalfoundries-pdk-libs-gf180mcu_fd_pr

  View on GitHub
  Primitives for GF180MCU provided by GlobalFoundries.
  ☆56Aug 28, 2023Updated 2 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities

  View on GitHub
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆20Aug 20, 2019Updated 6 years ago
• riscv / docs-spec-template

  View on GitHub
  ☆37Updated this week
• pulp-platform / serial_link

  View on GitHub
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆36Feb 24, 2026Updated last week
• verilator / uvm

  View on GitHub
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆31Oct 12, 2025Updated 4 months ago
• riscv-non-isa / riscv-semihosting

  View on GitHub
  ☆32Updated this week
• riscv-verification / riscvISACOV

  View on GitHub
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆34Dec 11, 2025Updated 2 months ago
• grayresearch / CX

  View on GitHub
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Jun 28, 2025Updated 8 months ago
• chiggs / UVM

  View on GitHub
  Mirror of the Universal Verification Methodology from sourceforge
  ☆37Jan 21, 2015Updated 11 years ago
• freecores / pipelined_fft_256

  View on GitHub
  Pipelined FFT/IFFT 256 points processor
  ☆10Jul 17, 2014Updated 11 years ago
• chipsalliance / riscv-fw-infrastructure

  View on GitHub
  SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...
  ☆31Dec 9, 2021Updated 4 years ago
• mohamed / fsm2sv

  View on GitHub
  SystemVerilog FSM generator
  ☆35May 5, 2024Updated last year
• jinwookjungs / lefdef_util

  View on GitHub
  A LEF/DEF Utility.
  ☆34Aug 15, 2019Updated 6 years ago
• freecores / ethernet_tri_mode

  View on GitHub
  10_100_1000 Mbps tri-mode ethernet MAC
  ☆10Jul 17, 2014Updated 11 years ago
• xinmeng / metahdl

  View on GitHub
  Language for simplifying parameterized RTL design
  ☆12Nov 6, 2024Updated last year
• riscv / virtual-memory

  View on GitHub
  ☆39Sep 15, 2021Updated 4 years ago
• mattbirman / Network-on-Chip-in-VHDL

  View on GitHub
  ☆20May 8, 2012Updated 13 years ago
• jetperch / pyjoulescope_examples

  View on GitHub
  Python scripting and programming examples using the joulescope package
  ☆14Feb 4, 2025Updated last year
• 9SQ / SECCON_TOWER_FONT

  View on GitHub
  SECCON塔フォント
  ☆10Feb 7, 2019Updated 7 years ago
• riscvarchive / riscv-zfinx

  View on GitHub
  ☆12Feb 15, 2024Updated 2 years ago
• nickdavidhaynes / FT232H_communication

  View on GitHub
  ☆11Jul 4, 2016Updated 9 years ago
• YigitDemirag / meta-analog

  View on GitHub
  JAX implementation of MAML on the analog spiking neural network accelerator for the edge adaptation
  ☆11Jan 26, 2023Updated 3 years ago
• AndroPlus-org / magisk-module-c330-gsi

  View on GitHub
  Rakuten Mini C330 で Android 10 GSI を起動する際のブートループを修正します。※data初期化後は、一旦ブートループして一瞬Hi thereが出る画面まで進んでからTWRPを起動すればインストールできるようになります
  ☆10Aug 15, 2020Updated 5 years ago
• RISCV-on-Microsemi-FPGA / M2GL025-Creative-Board

  View on GitHub
  Igloo2 M2GL025 Creative Development Board
  ☆11Oct 15, 2019Updated 6 years ago
• ponylang / crypto

  View on GitHub
  Library of common cryptographic algorithms and functions for Pony
  ☆12Jul 16, 2025Updated 7 months ago
• Mi-V-Soft-RISC-V / miv-rv32-bare-metal-examples

  View on GitHub
  ☆13Aug 7, 2025Updated 7 months ago