A simple MOSFET model with only 5-DC-parameters for circuit simulation
☆50Sep 8, 2025Updated 5 months ago
Alternatives and similar repositories for MOSFET_model
Users that are interested in MOSFET_model are comparing it to the libraries listed below
Sorting:
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated 2 months ago
- Circuit Automatic Characterization Engine☆52Feb 7, 2025Updated last year
- Parasitic Extraction for KLayout☆39Feb 20, 2026Updated last week
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆25Jan 14, 2026Updated last month
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆77Mar 28, 2025Updated 11 months ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:☆677Feb 17, 2026Updated last week
- ☆59Jul 11, 2025Updated 7 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆315Oct 22, 2025Updated 4 months ago
- Open-source PDK version manager☆39Nov 25, 2025Updated 3 months ago
- Reinforcement learning assisted analog layout design flow.☆34Jul 29, 2024Updated last year
- EM simulation scripts to simulate passive devices on Skywater 130nm open-source process. (Octave interface only for now)☆13Jan 7, 2024Updated 2 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆39Jun 10, 2021Updated 4 years ago
- Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.☆30Jul 30, 2022Updated 3 years ago
- Hdl21 Schematics☆16Jan 24, 2024Updated 2 years ago
- Primitives for GF180MCU provided by GlobalFoundries.☆56Aug 28, 2023Updated 2 years ago
- MOSIS MPW Test Data and SPICE Models Collections☆39Apr 2, 2020Updated 5 years ago
- An innovative Verilog-A compiler - reloaded☆38Updated this week
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆51Mar 13, 2025Updated 11 months ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 2 weeks ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated 10 months ago
- Primitives for SKY130 provided by SkyWater.☆37Mar 9, 2024Updated last year
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- An innovative Verilog-A compiler☆181Aug 20, 2024Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆79Jan 25, 2026Updated last month
- ☆58Mar 31, 2025Updated 11 months ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 6 years ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆444Updated this week
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆34Jun 22, 2025Updated 8 months ago
- ☆14May 24, 2025Updated 9 months ago
- ☆338Jan 13, 2026Updated last month
- ☆26Dec 4, 2025Updated 2 months ago
- ☆86Jan 15, 2025Updated last year
- An open-source 555 timer☆23Aug 27, 2024Updated last year
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated 2 years ago
- Hardware Description Library☆87Feb 17, 2026Updated last week
- A tiny Python package to parse spice raw data files.☆53Dec 26, 2022Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆38Jan 13, 2023Updated 3 years ago