lf-lang / playground-lingua-francaLinks
Try Lingua Franca now!
☆20Updated 3 weeks ago
Alternatives and similar repositories for playground-lingua-franca
Users that are interested in playground-lingua-franca are comparing it to the libraries listed below
Sorting:
- Intuitive concurrent programming in any language☆274Updated this week
- Xronos revolutionizes robotics software — enabling reproducible behavior, timing control, and rapid root cause analysis through built-in …☆15Updated 2 weeks ago
- Unified Access Page for the TRISTAN project☆19Updated this week
- An Eclipse 4 RCP based GUI to interact with SystemC simulators☆10Updated 2 weeks ago
- A reactor runtime written in C☆19Updated this week
- The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the deve…☆56Updated 9 months ago
- Blazingly fast, modern C++ API using coroutines for efficient RTL verification and co-simulation via the VPI interface☆17Updated last month
- Collection of Yocto Project layers to enable AMD Xilinx products☆167Updated 2 weeks ago
- RISC-V Verification Interface☆107Updated 2 weeks ago
- SystemC Configuration, Control and Inspection (CCI)☆17Updated this week
- Framework Open EDA Gui☆69Updated 10 months ago
- RISC-V Virtual Prototype☆44Updated 4 years ago
- tcl scripts used to build or generate vivado projects automatically☆33Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆232Updated last month
- This shows a simple ARM bare-metal software implementation for gem5☆18Updated 4 years ago
- SystemC Common Practices (SCP)☆31Updated 10 months ago
- ROS 2 Hardware Acceleration Working Group community governance model & list of projects☆65Updated last year
- ☆12Updated 5 months ago
- FPGA and Digital ASIC Build System☆78Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆47Updated last year
- Universal Memory Interface (UMI)☆153Updated last week
- HDL symbol generator☆194Updated 2 years ago
- Communication framework for RTL simulation and emulation.☆301Updated this week
- Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.☆66Updated last month
- Constrained random stimuli generation for C++ and SystemC☆53Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆13Updated 3 weeks ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated last week
- A Python package to use FPGA development tools programmatically.☆139Updated 6 months ago