Alternatives and similar repositories for beri

Users that are interested in beri are comparing it to the libraries listed below

• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 10 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆55Updated 5 years ago
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆58Updated 6 months ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 7 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 6 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 8 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last week
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 12 years ago
• CTSRD-CHERI / axe
  Consistency checker for memory subsystem traces
  ☆19Updated 8 years ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆66Updated 5 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago