Alternatives and similar repositories for beri:

Users that are interested in beri are comparing it to the libraries listed below

• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆41Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆18Updated 5 years ago
• pretis / flexpret
  A time-predictable processor for mixed-criticality systems
  ☆57Updated 2 months ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 10 months ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆72Updated 5 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• chipy-hdl / chipy
  chipy hdl
  ☆17Updated 6 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆25Updated 4 years ago
• sifive / last-week-in-risc-v
  Weekly RISC-V Newsletter
  ☆28Updated 6 years ago
• sifive / RiscvSpecFormal
  The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, mod…
  ☆76Updated 4 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆21Updated 8 years ago
• CTSRD-CHERI / axe
  Consistency checker for memory subsystem traces
  ☆14Updated 8 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• acjf3 / l3mips
  L3 based MIPS specification and emulator
  ☆15Updated 3 years ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 5 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆31Updated 9 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆30Updated 2 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆41Updated 7 years ago