tomahawkins / verilog
A Verilog parser for Haskell.
☆34Updated 3 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below
Sorting:
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Kansas Lava☆47Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last week
- Intel 8080 CPU core: software emulator and CLaSH hardware description☆27Updated 2 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Yosys plugin for synthesis of Bluespec code☆15Updated 3 years ago
- chipy hdl☆17Updated 7 years ago
- L3 based MIPS specification and emulator☆15Updated 3 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Deploying Haskell to Lattice iCE40 using fully open source toolchain☆13Updated 8 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- RISC-V BSV Specification☆20Updated 5 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 7 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Galois RISC-V ISA Formal Tools☆58Updated last month
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Netlist and Verilog Haskell Package☆18Updated 14 years ago
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- ☆29Updated 4 years ago
- 32-bit RISC-V Emulator☆24Updated 6 years ago
- ☆14Updated last year
- Generate interface between Clash and Verilator☆22Updated last year