tomahawkins / verilogLinks
A Verilog parser for Haskell.
☆34Updated 3 years ago
Alternatives and similar repositories for verilog
Users that are interested in verilog are comparing it to the libraries listed below
Sorting:
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Kansas Lava☆47Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆28Updated last month
- Intel 8080 CPU core: software emulator and CLaSH hardware description☆27Updated 2 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- chipy hdl☆17Updated 7 years ago
- Deploying Haskell to Lattice iCE40 using fully open source toolchain☆13Updated 9 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 4 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- 32-bit RISC-V Emulator☆24Updated 6 years ago
- A bit-serial CPU☆19Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆24Updated 7 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- ☆29Updated 4 years ago
- The BERI and CHERI processor and hardware platform☆50Updated 8 years ago
- L3 based MIPS specification and emulator☆15Updated 3 years ago
- A RiscV processor implementing the RV32I instruction set written in Clash☆53Updated 7 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- ☆14Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Netlist and Verilog Haskell Package☆18Updated 14 years ago
- ☆17Updated last year
- PicoRV☆44Updated 5 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- ☆21Updated 9 years ago
- Yosys plugin for synthesis of Bluespec code☆15Updated 3 years ago
- Galois RISC-V ISA Formal Tools☆58Updated 2 months ago
- Generate interface between Clash and Verilator☆22Updated last year