Alternatives and similar repositories for verilog

Users that are interested in verilog are comparing it to the libraries listed below

• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆29Updated 2 weeks ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• ku-fpg / kansas-lava
  Kansas Lava
  ☆49Updated 5 years ago
• thoughtpolice / rv32-sail
  32-bit RISC-V Emulator
  ☆26Updated 6 years ago
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆25Updated 7 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• gergoerdi / clash-intel8080
  Intel 8080 CPU core: software emulator and CLaSH hardware description
  ☆28Updated 2 years ago
• thoughtpolice / yosys-bluespec
  Yosys plugin for synthesis of Bluespec code
  ☆15Updated 4 years ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 9 years ago
• SiliconSemantics / firrtlator
  firrtlator is a FIRRTL C++ library
  ☆23Updated 8 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated this week
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 8 months ago
• mgajda / clash-yosys-demo
  Deploying Haskell to Lattice iCE40 using fully open source toolchain
  ☆13Updated 9 years ago
• m-labs / microscope
  Finding the bacteria in rotting FPGA designs.
  ☆14Updated 4 years ago
• blarney-lang / blarney
  Haskell library for hardware description
  ☆104Updated last month
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• ArcaneNibble / project-chibi
  Altera MAX V bitstream documentation -- CLEANUP PENDING
  ☆19Updated 5 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 13 years ago
• christiaanb / contranomy
  ☆30Updated 4 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• cbiffle / cfm
  A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.
  ☆58Updated 4 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆23Updated 4 months ago