The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
☆139Jul 11, 2025Updated last year
Alternatives and similar repositories for cva5
Users that are interested in cva5 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆162Oct 31, 2024Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆240Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆279Nov 6, 2024Updated last year
- Open-source non-blocking L2 cache☆66Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆120Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆627Updated this week
- CORE-V Family of RISC-V Cores☆371Mar 31, 2026Updated 5 months ago
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated last month
- The multi-core cluster of a PULP system.☆116Aug 4, 2026Updated last month
- RISC-V CPU Core☆449Jun 24, 2025Updated last year
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆173Updated this week
- VeeR EH1 core☆967Jul 16, 2026Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆116Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆212Sep 2, 2026Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,308Sep 18, 2021Updated 5 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆101Aug 20, 2026Updated 3 weeks ago
- Simple runtime for Pulp platforms☆55Jul 7, 2026Updated 2 months ago
- Open source FPGA-based NIC and platform for in-network compute☆18May 22, 2024Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,291Aug 26, 2026Updated 3 weeks ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆303Updated this week
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆76May 15, 2023Updated 3 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 8 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- Yet Another RISC-V Implementation☆101Sep 21, 2024Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆548Aug 19, 2026Updated 3 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,701Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆681Sep 8, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- Advanced Architecture Labs with CVA6☆83Jan 16, 2024Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,120Updated this week
- Common SystemVerilog components☆799Updated this week
- VeeR EH2 core☆279Updated this week
- ☆326Jan 23, 2026Updated 7 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,062Updated this week