The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
☆72Oct 9, 2026Updated 2 weeks ago
Alternatives and similar repositories for cve2
Users that are interested in cve2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆287Nov 6, 2024Updated last year
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆17Sep 18, 2026Updated last month
- Unified RISC-V Access Platform (UAP) project repository☆29Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,317Oct 20, 2026Updated last week
- RISC-V Functional ISA Simulator☆20May 28, 2026Updated 5 months ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆308Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆139Jul 11, 2025Updated last year
- ☆16Oct 5, 2026Updated 3 weeks ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆26Sep 10, 2026Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆294Updated this week
- ☆19Jul 2, 2020Updated 6 years ago
- Post Quantum Cryptography☆16Oct 19, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆10Aug 1, 2025Updated last year
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆501May 8, 2026Updated 5 months ago
- Repository that maintain the OpenBus Interface spec☆24Apr 26, 2023Updated 3 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,135Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆20Jul 16, 2026Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆250Updated this week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆64Sep 28, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆382Dec 2, 2025Updated 10 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆733Oct 19, 2026Updated last week
- Simple UVM environment for experimenting with Verilator.☆56Sep 9, 2026Updated last month
- ☆13Jun 10, 2026Updated 4 months ago
- AIA IP compliant with the RISC-V AIA spec☆47Sep 7, 2026Updated last month
- ☆10Nov 2, 2023Updated 2 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,171Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆657Updated this week
- UNSUPPORTED INTERNAL toolchain builds☆49Sep 13, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- matrix-coprocessor for RISC-V☆40Feb 27, 2026Updated 8 months ago
- RISC-V Worlds provides isolation in a hardware platform by constraining access to system physical addresses.☆15Aug 12, 2026Updated 2 months ago
- Documentation for IHP 130nm BiCMOS Open Source PDK☆10Oct 14, 2026Updated 2 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆95Apr 1, 2026Updated 6 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆214Oct 19, 2026Updated last week
- RISC-V fast interrupt controller☆35Aug 6, 2026Updated 2 months ago
- The OpenPiton Platform☆32May 22, 2023Updated 3 years ago