sylefeb / SilixelLinks
Exploring gate level simulation
☆58Updated 9 months ago
Alternatives and similar repositories for Silixel
Users that are interested in Silixel are comparing it to the libraries listed below
Sorting:
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- Experiments with Yosys cxxrtl backend☆50Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- An FPGA reverse engineering and documentation project☆64Updated last week
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- PicoRV☆43Updated 5 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- A pipelined RISC-V processor☆63Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆98Updated last year
- RISC-V out-of-order core for education and research purposes☆81Updated last week
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Updated last year
- Virtual Development Board☆64Updated 4 years ago
- CoreScore☆171Updated 2 months ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated 3 weeks ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆32Updated 4 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 4 years ago
- Doom classic port to lightweight RISC‑V☆107Updated 3 years ago
- ☆33Updated 3 years ago
- Industry standard I/O for Amaranth HDL☆31Updated last year
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Updated last year