Exploring gate level simulation
☆58Apr 23, 2025Updated 11 months ago
Alternatives and similar repositories for Silixel
Users that are interested in Silixel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Nov 21, 2020Updated 5 years ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆17Feb 16, 2024Updated 2 years ago
- ☆20Dec 23, 2020Updated 5 years ago
- Bit streams forthe Ulx3s ECP5 device☆18Apr 9, 2023Updated 2 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆94Mar 12, 2026Updated last week
- ☆45Jan 5, 2023Updated 3 years ago
- CoreScore☆172Nov 14, 2025Updated 4 months ago
- ☆15May 17, 2025Updated 10 months ago
- Retro computing on the Ulx3s ECP5 FPGA board☆25Mar 3, 2022Updated 4 years ago
- Small 32-bit RISC-V CPU with a half-width datapath inspired by the 68000☆16Dec 21, 2023Updated 2 years ago
- PLEASE MOVE TO PAWSv2☆16Feb 2, 2022Updated 4 years ago
- Generate Zynq configurations without using the vendor GUI☆30Jul 5, 2023Updated 2 years ago
- Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs☆33Jul 15, 2021Updated 4 years ago
- ☆21Mar 8, 2021Updated 5 years ago
- IceCore Ice40 HX based modular core☆47Jan 23, 2021Updated 5 years ago
- design and verification of asynchronous circuits☆44Feb 27, 2026Updated 3 weeks ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- Yet Another Debug Transport☆25Dec 3, 2025Updated 3 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- 2-layer and 4-layer FPGA development board with ZYNQ 7010/7020 400-pin BGA.☆20Jan 6, 2026Updated 2 months ago
- assorted library of utility cores for amaranth HDL☆103Sep 17, 2024Updated last year
- Playground for experimenting with and sharing short Amaranth programs on the web☆21Oct 26, 2025Updated 4 months ago
- ☆34Feb 3, 2021Updated 5 years ago
- A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw☆123Sep 26, 2022Updated 3 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆14Jan 15, 2024Updated 2 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 4 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32May 15, 2023Updated 2 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- A few minimal bare-metal "hello, world" programs to help learn about the GD32VF103 RISC-V microcontroller without relying on a particular…☆28Feb 27, 2020Updated 6 years ago
- Some materials and sample source for RV32 OS projects.☆22May 31, 2022Updated 3 years ago
- Kakao Linux☆39May 30, 2025Updated 9 months ago
- Wireless USB Disk for Pendrive S3☆18Jul 11, 2024Updated last year
- Soft USB for LiteX☆51Oct 6, 2025Updated 5 months ago
- Open source Logic Analyzer based on LiteX SoC☆27Apr 12, 2025Updated 11 months ago
- AMD Generic Encapsulated Software Architecture Platform Security Processor Configuration Block manipulation library☆16Dec 18, 2025Updated 3 months ago
- Riegel Computer☆17Jun 30, 2023Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year