Alternatives and similar repositories for sudoku-challenge

Users that are interested in sudoku-challenge are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆20Updated 6 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 6 months ago
• The-OpenROAD-Project / megaboom
  ☆25Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated 2 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 3 weeks ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆31Updated 2 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last week
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆26Updated 3 months ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆19Updated 2 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆53Updated this week
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆28Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆48Updated last month
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 months ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago