vmunoz82 / sudoku-challenge
Solving Sudokus using open source formal verification tools
☆15Updated 2 years ago
Alternatives and similar repositories for sudoku-challenge:
Users that are interested in sudoku-challenge are comparing it to the libraries listed below
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆17Updated last year
- ☆24Updated this week
- ☆20Updated 2 months ago
- Open Source Verification Bundle for VHDL and System Verilog☆43Updated last year
- End-to-End Open-Source I2C GPIO Expander☆29Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- ☆36Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆40Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated this week
- ☆33Updated 2 years ago
- ☆19Updated last year
- ☆58Updated 3 years ago
- Open FPGA Modules☆23Updated 3 months ago
- Wishbone interconnect utilities☆38Updated 7 months ago
- A padring generator for ASICs☆24Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆28Updated this week
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆51Updated last month
- ☆39Updated 2 years ago
- LunaPnR is a place and router for integrated circuits☆45Updated last month
- A current mode buck converter on the SKY130 PDK☆26Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆35Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated 4 months ago
- Extensible FPGA control platform☆55Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A compact, configurable RISC-V core☆11Updated last month
- LibreSilicon's Standard Cell Library Generator☆18Updated 8 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago