vmunoz82 / sudoku-challengeLinks
Solving Sudokus using open source formal verification tools
☆17Updated 3 years ago
Alternatives and similar repositories for sudoku-challenge
Users that are interested in sudoku-challenge are comparing it to the libraries listed below
Sorting:
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆117Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆61Updated last year
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆55Updated 4 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆46Updated 2 months ago
- End-to-End Open-Source I2C GPIO Expander☆33Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆105Updated last week
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- Framework Open EDA Gui☆68Updated 8 months ago
- A current mode buck converter on the SKY130 PDK☆29Updated 4 years ago
- Wishbone interconnect utilities☆41Updated 6 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 4 months ago
- Drawio => VHDL and Verilog☆57Updated last year
- ☆33Updated 2 years ago
- ☆39Updated 2 years ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- Raptor end-to-end FPGA Compiler and GUI☆84Updated 8 months ago
- ☆38Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆36Updated 2 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆141Updated 2 years ago
- A flexible and scalable development platform for modern FPGA projects.☆32Updated this week