Alternatives and similar repositories for sudoku-challenge

Users that are interested in sudoku-challenge are comparing it to the libraries listed below

• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆20Updated 2 years ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆59Updated 3 weeks ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆30Updated 4 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆53Updated 3 months ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated last week
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆64Updated last week
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆71Updated 2 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 3 years ago
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆33Updated last month
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 5 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆49Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated last week
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 9 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆84Updated 9 months ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆56Updated 2 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated last week
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆47Updated 3 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago