tomverbeure / jtag_uart_exampleLinks
Mini CPU design with JTAG UART support
☆20Updated 4 years ago
Alternatives and similar repositories for jtag_uart_example
Users that are interested in jtag_uart_example are comparing it to the libraries listed below
Sorting:
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆19Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆12Updated 2 years ago
- Example designs for the Spartan7 "S7 Mini" FPGA board☆28Updated 6 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 5 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Use ECP5 JTAG port to interact with user design☆29Updated 3 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆17Updated 3 years ago
- simple wishbone client to read buttons and write leds☆18Updated last year
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- mystorm sram test☆27Updated 7 years ago
- There are many RISC V projects on iCE40. This one is mine.☆15Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆24Updated 6 years ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Firmware to implement USB communications on the CH32V307 microcontroller☆11Updated 2 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- ☆16Updated 3 years ago
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 4 years ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14Updated 5 years ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆15Updated last year
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- nMigen examples for the ULX3S board☆16Updated 4 years ago
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆21Updated 3 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated 2 weeks ago