Mini CPU design with JTAG UART support
☆21Jun 8, 2021Updated 5 years ago
Alternatives and similar repositories for jtag_uart_example
Users that are interested in jtag_uart_example are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- How to use the Intel JTAG primitive without using virtual JTAG☆17Oct 31, 2021Updated 4 years ago
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated 11 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆17Apr 7, 2022Updated 4 years ago
- Gateware for the Terasic/Arrow DECA board, to become a USB2 high speed audio interface☆22Feb 28, 2022Updated 4 years ago
- PS/2 keyboard/mouse converter for old Silicon Graphics computers.☆17Mar 27, 2025Updated last year
- ☆17Apr 17, 2021Updated 5 years ago
- Run an executable from RAM on a Bouffalo MCU (BL602 or BL808)☆25Jan 18, 2023Updated 3 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- ☆20Feb 23, 2022Updated 4 years ago
- Verilog re-implementation of the famous CAPCOM arcade game☆29Jan 25, 2019Updated 7 years ago
- Development Kit☆35Apr 23, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL simulation model for PADAUK PDK microcontrollers☆22May 20, 2020Updated 6 years ago
- Tutorial and example projects for the Arrow MAX1000 FPGA board☆57Jun 24, 2024Updated 2 years ago
- ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor☆13Dec 13, 2021Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- Altera JTAG UART wrapper for Bluespec☆26Mar 27, 2014Updated 12 years ago
- Tutorial and example projects for the Arrow MAX1000 FPGA board☆14Sep 13, 2018Updated 7 years ago
- Spins of Grant Searle's MultiComp project on various hardware☆77May 31, 2023Updated 3 years ago
- Official code for "CSCE-Net: Cross-Scale Context Extracted Hashing for Fine-Grained Image Binary Encoding"☆12Jun 1, 2023Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆192Mar 10, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- LiteX LUNA USB stack integration☆14Jun 12, 2022Updated 4 years ago
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆21May 30, 2019Updated 7 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Jun 7, 2015Updated 11 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆107Aug 28, 2025Updated 10 months ago
- CoreScore☆178Jun 9, 2026Updated last month
- A Nhost Starter Project Using React Native☆13Jan 26, 2023Updated 3 years ago
- Python GUI for UrJTAG library.☆22Mar 6, 2026Updated 4 months ago
- RTL-SDR 433MHz signal recovery with MATLAB☆12Feb 13, 2015Updated 11 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- C++ SystemC Implementation of a Systolic Array☆16May 15, 2020Updated 6 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆92Apr 8, 2024Updated 2 years ago
- (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…☆28Feb 7, 2023Updated 3 years ago
- A driver for the XPT2046 touchScreen driver for STM32.☆12Dec 4, 2021Updated 4 years ago
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Outdated. See https://github.com/saleae/jtag-analyzer for the official Saleae JTAG Analyzer☆12May 21, 2018Updated 8 years ago
- Tài liệu gửi trước chuẩn bị cho chương trình Trại hè Toán và Khoa học MaSSP 2018.☆14Aug 17, 2018Updated 7 years ago