Alternatives and similar repositories for subservient

Users that are interested in subservient are comparing it to the libraries listed below

• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last month
• aignacio / nox
  RISC-V Nox core
  ☆66Updated last week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆98Updated last week
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 4 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆63Updated 2 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆23Updated 2 months ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 3 weeks ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 3 months ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆21Updated 2 years ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆48Updated 3 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆81Updated 5 years ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆82Updated 7 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆61Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago