Alternatives and similar repositories for subservient

Users that are interested in subservient are comparing it to the libraries listed below

• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆109Updated 3 weeks ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated last month
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆30Updated last month
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆23Updated 2 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 6 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• b224hisl / rioschip
  ☆33Updated 3 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 5 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 2 months ago