Alternatives and similar repositories for subservient

Users that are interested in subservient are comparing it to the libraries listed below

• efabless / sky130_sram_macros_old
  ☆37Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 2 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last month
• aignacio / nox
  RISC-V Nox core
  ☆65Updated 3 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆64Updated 5 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 3 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 2 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆89Updated 6 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated this week
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆57Updated 7 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆21Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated last week
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆83Updated 7 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆78Updated 4 years ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆62Updated 2 years ago
• pulp-platform / svase
  ☆32Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 months ago