olofk / subservient
Small SERV-based SoC primarily for OpenMPW tapeout
☆35Updated last year
Related projects ⓘ
Alternatives and complementary repositories for subservient
- ☆36Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- An automatic clock gating utility☆43Updated 4 months ago
- RISC-V Nox core☆61Updated 3 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆30Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- A SystemVerilog source file pickler.☆52Updated last month
- ☆52Updated 2 years ago
- Announcements related to Verilator☆38Updated 4 years ago
- FPGA250 aboard the eFabless Caravel☆27Updated 3 years ago
- Demo SoC for SiliconCompiler.☆52Updated 3 weeks ago
- ☆57Updated 3 years ago
- Open FPGA Modules☆23Updated last month
- Platform Level Interrupt Controller☆35Updated 6 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- ☆33Updated 2 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- ☆22Updated last year
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- KLayout technology files for ASAP7 FinFET educational process☆18Updated last year
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- SystemVerilog frontend for Yosys☆51Updated this week
- Wishbone interconnect utilities☆37Updated 6 months ago
- ☆29Updated 2 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆26Updated last month
- Bitstream relocation and manipulation tool.☆40Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago