Alternatives and similar repositories for liguoqi-rv64-cpu

Users that are interested in liguoqi-rv64-cpu are comparing it to the libraries listed below

• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆31Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 8 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆22Updated 9 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• 1932287243 / NPC_IDE
  This is an IDE for YSYX_NPC debuging
  ☆12Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• msyksphinz-self / riscv-vector-tests
  Original test vector of RISC-V Vector Extension
  ☆14Updated 4 years ago
• RPTU-EIS / RISCV-Core
  5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
  ☆13Updated last month
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 3 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆31Updated this week
• sequencer / arithmetic
  ☆33Updated 9 months ago
• OSCPU / chisel-playground
  ☆70Updated 11 months ago
• LvNA-system / EasyDiff-noop
  ☆10Updated 6 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated 2 weeks ago
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆16Updated last year
• oscc-web / ysyx-website
  The official website of One Student One Chip project.
  ☆11Updated last month
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆75Updated last week
• xiaoan109 / ysyx-workbench
  一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
  ☆22Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• Jpz-sdju / trinity
  ☆32Updated 5 months ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆46Updated 2 years ago
• scutdig / PyChip-py-hcl
  A Hardware Construct Language
  ☆44Updated 3 years ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆46Updated last month
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• lingscale / cc01
  ☆30Updated 10 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago