nvdla / qbox
NVDLA modifications for GreenSocs qbox (https://git.greensocs.com/qemu/qbox)
☆19Updated 6 years ago
Related projects: ⓘ
- ☆19Updated this week
- QEMU libsystemctlm-soc co-simulation demos.☆117Updated 3 months ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆9Updated last year
- PCI Express controller model☆41Updated last year
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆14Updated 11 years ago
- Archives of SystemC from The Ground Up Book Exercises☆27Updated last year
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆21Updated last year
- The multi-core cluster of a PULP system.☆55Updated this week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆23Updated 2 weeks ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆44Updated this week
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆52Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- ☆42Updated 2 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆61Updated 2 months ago
- Support for Rocket Chip on Zynq FPGAs☆39Updated 5 years ago
- SoCRocket - Core Repository☆32Updated 7 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆16Updated 6 years ago
- SystemC training aimed at TLM.☆24Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆74Updated 3 weeks ago
- RISC-V Nexus Trace TG documentation and reference code☆39Updated this week
- RISC-V Virtual Prototype☆35Updated 2 years ago
- ☆44Updated 3 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆85Updated 3 weeks ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆39Updated 3 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆44Updated 7 years ago
- ☆40Updated 3 months ago