gh-code / libCircuit

Related projects: ⓘ

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆24Updated 3 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 3 weeks ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆19Updated 4 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆14Updated 4 months ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆27Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆38Updated 4 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆53Updated 2 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆19Updated 2 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated last month
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 7 years ago
• levibyte / channel_router
  demo on simple channel router
  ☆12Updated 5 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆25Updated 2 years ago
• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆15Updated 3 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆33Updated 3 years ago
• ashleyjr / Verilog
  ☆10Updated 5 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆27Updated 3 weeks ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆20Updated 5 years ago
• idea-fasoc / fasoc
  ☆52Updated 11 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• efabless / proton
  ☆28Updated 4 years ago
• clin99 / awesome-eda
  ☆87Updated 5 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆15Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆34Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆42Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆52Updated 7 years ago
• RIOSMPW / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆38Updated 4 months ago