libCircuit is a C++ Library for EDA software development
☆18Sep 27, 2018Updated 7 years ago
Alternatives and similar repositories for libCircuit
Users that are interested in libCircuit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SwapForth J1a processor for Icestudio☆12Aug 28, 2020Updated 5 years ago
- verilog example to drive PCM5102 DAC with FPGA☆19Apr 30, 2018Updated 8 years ago
- A Javascript library for generating blocks for the ICEstudio FPGA development environment☆10Jul 31, 2018Updated 7 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- Flute 3.1 with CMake support☆14Jul 25, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Colecciones para el tutorial Electrónica digital para Makers con FPGAs Libres☆11Dec 4, 2018Updated 7 years ago
- SAT-based ATPG using TG-Pro model☆19Jun 5, 2018Updated 7 years ago
- Combinational ATPG generator based on D-Algorithm☆16Nov 25, 2020Updated 5 years ago
- OpenFPGA☆34Mar 12, 2018Updated 8 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA☆16Oct 11, 2018Updated 7 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- Dual MikroBUS board for Upduino 2 FPGA☆18May 24, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- Primer Seek in RNA-Seq. Designs RT-PCR primers that validate alternative splicing events from RNA-Seq data.☆13Nov 27, 2016Updated 9 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- Verilog parsing and generator crate.☆22Apr 16, 2020Updated 6 years ago
- An example of how How to access native libraries in Flutter using Dart FFI☆14Jan 25, 2022Updated 4 years ago
- Free open source EDA tools☆66Oct 1, 2019Updated 6 years ago
- C++ implement a simple CNN framework to train mnist data. Done!☆10Mar 29, 2022Updated 4 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FreedomBox version of Privoxy☆55May 9, 2015Updated 11 years ago
- A Chisel implementation for an FPGA Pin Finder thru UART☆17Sep 24, 2024Updated last year
- Realization of Lane Detection on CPU and implementation on FPGA using SDSOC and VIVADO. Key terms for used softwares: C++, OpenCV, xfOpe…☆20Apr 13, 2020Updated 6 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- A repo of basic Verilog/SystemVerilog modules useful in other circuits.☆21Nov 18, 2017Updated 8 years ago
- Curso de 35h sobre el diseño de sistemas digitales usando FPGAs libres, orientado para makers☆19Jul 4, 2017Updated 8 years ago
- 自建 chisel 工程模板☆15Jul 19, 2023Updated 2 years ago
- A fast, small, efficient pthreads based threadpool in c☆16Mar 2, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- FEMM & Matlab Simulation & TI C2000 DSP code for control of switched reluctance machine in Motor and Generator Mode☆13Sep 28, 2018Updated 7 years ago
- Modbus block on FPGA☆14Jul 24, 2020Updated 5 years ago
- Instructions and packages for Zybo compatibility to Pynq☆16Dec 10, 2018Updated 7 years ago
- A verilog parser☆19Apr 12, 2024Updated 2 years ago
- iTunes U browser for non-{Mac,Windows} operating systems☆24Oct 14, 2022Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago