secworks / cmacLinks
Implementation of the CMAC keyed hash function using AES as block cipher.
☆16Updated 7 months ago
Alternatives and similar repositories for cmac
Users that are interested in cmac are comparing it to the libraries listed below
Sorting:
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆114Updated this week
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Mutation Cover with Yosys (MCY)☆88Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 5 months ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 5 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Code used in☆198Updated 8 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- True Random Number Generator core implemented in Verilog.☆76Updated 5 years ago
- SystemVerilog synthesis tool☆216Updated 7 months ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆391Updated 7 months ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Main page☆128Updated 5 years ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- Build Customized FPGA Implementations for Vivado☆341Updated this week
- FPGA tool performance profiling☆102Updated last year
- FuseSoC standard core library☆147Updated 5 months ago
- Verilog Configurable Cache☆184Updated 3 weeks ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- A SystemVerilog source file pickler.☆60Updated last year
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆104Updated 6 years ago
- ☆80Updated last year
- Experimental flows using nextpnr for Xilinx devices☆245Updated last year