secworks / cmacLinks
Implementation of the CMAC keyed hash function using AES as block cipher.
☆16Updated 8 months ago
Alternatives and similar repositories for cmac
Users that are interested in cmac are comparing it to the libraries listed below
Sorting:
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Main page☆129Updated 5 years ago
- HW Design Collateral for Caliptra RoT IP☆124Updated last week
- Yet Another RISC-V Implementation☆99Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 7 months ago
- ☆87Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 4 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Open-source FPGA research and prototyping framework.☆210Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- FuseSoC standard core library☆151Updated 3 weeks ago
- SystemVerilog synthesis tool☆221Updated 9 months ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- Hardware generator debugger☆77Updated last year
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆137Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆152Updated last month
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- A home for Genesis2 sources.☆43Updated 5 months ago
- A SystemVerilog language server based on the Slang library.☆97Updated this week
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- RISC-V Formal Verification Framework☆173Updated last week