Alternatives and similar repositories for interview_digital_IC

Users that are interested in interview_digital_IC are comparing it to the libraries listed below

• programer-guan / digital_ic_verification
  数字IC验证案例（SV and UVM）
  ☆26Updated 4 years ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆12Updated 2 years ago
• ayzk / Simulator_CPU
  Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
  ☆20Updated 4 years ago
• Lydaidai / The-car-base-on-FPGA
  开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…
  ☆14Updated 6 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆105Updated 4 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 3 years ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆159Updated 3 years ago
• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆11Updated 11 months ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆62Updated 6 years ago
• Ams0x57 / Digital_Adders_Verilog
  32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…
  ☆27Updated 7 years ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆41Updated 4 years ago
• Swingfal1 / booth_multiplier_radix_4
  Verilog program
  ☆16Updated 5 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated last week
• sazczmh / PYNQ_Workshop
  ☆38Updated 6 years ago
• Grootzz / Verilog-FIR
  FIR implemention with Verilog
  ☆50Updated 6 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆58Updated 2 years ago
• Shahriar-0 / Digital-Logic-Design-Lab-Experiments-S2023
  Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
  ☆11Updated last year
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 13 years ago
• xupsh / pp4fpgas-cn-hls
  HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
  ☆241Updated 4 years ago
• qninth / awesome-digital-ic
  A collection of great digital IC project/tutorial/website etc..
  ☆133Updated 3 years ago
• tharunchitipolu / sobel-edge-detector
  Sobel is first order or gradient based edge operator for images and it is implemented using verilog.
  ☆14Updated 5 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• LaErre9 / Zynq_Ultrascale_Vitis_AI_CNN_ZCU102
  Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…
  ☆18Updated last year
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆176Updated 3 years ago
• tangshi706 / Learning-materials
  IC设计中的一些经典书籍
  ☆12Updated 5 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆56Updated 6 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆69Updated 5 years ago
• jerrylioon / Solutions-to-HDLbits-Verilog-sets
  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
  ☆93Updated 2 years ago
• louisliuwei / PynqDocs
  PYNQ学习资料
  ☆173Updated 6 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆209Updated 2 years ago