zengchenglong / interview_digital_IC
关于数字IC的笔试面试题
☆9Updated 5 years ago
Alternatives and similar repositories for interview_digital_IC:
Users that are interested in interview_digital_IC are comparing it to the libraries listed below
- 数字IC验证案例(SV and UVM)☆26Updated 3 years ago
- A collection of possible interview questions for ASIC PD position☆19Updated 4 years ago
- 数字IC设计 学习笔记☆129Updated 3 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆17Updated 5 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆59Updated 6 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆83Updated 3 years ago
- Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…☆16Updated last year
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆11Updated last year
- Hardware implementation of HDR image producing algorithm☆16Updated 2 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆191Updated 2 years ago
- ☆39Updated 6 years ago
- 数字IC秋招项目、手撕代码☆34Updated last year
- 为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。☆23Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- upgrade to e203 (a risc-v core)☆42Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆176Updated last year
- FIR implemention with Verilog☆47Updated 5 years ago
- ☆144Updated 2 months ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆13Updated 3 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆51Updated last year
- ☆36Updated 4 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- Collect some IC textbooks for learning.☆134Updated 2 years ago
- FFT generator using Chisel☆58Updated 3 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago