yiwangchunyu / AI-RISC

Related projects ⓘ

Alternatives and complementary repositories for AI-RISC

• dldldlfma / eyeriss_v1
  ☆11Updated 5 years ago
• niexun / LSTM
  LSTM neural network (verilog)
  ☆11Updated 5 years ago
• zhehaoxu / ai-talk
  关于深度学习算法、框架、编译器、加速器的一些理解
  ☆13Updated 2 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆32Updated 2 months ago
• dldldlfma / super_small_toy_tpu
  ☆13Updated 3 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆12Updated 3 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆29Updated 4 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆47Updated 4 years ago
• WenqiJiang / FPGA-Based-RNN-Accelerator-Using-Vivado-HLS
  This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …
  ☆21Updated 5 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆23Updated last year
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆11Updated 3 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆63Updated last year
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆129Updated 4 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆26Updated 2 years ago
• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆29Updated 5 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆29Updated 5 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆10Updated 3 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆88Updated 6 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆24Updated 3 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆20Updated last year
• VGuoGavin / Hand-Writing-Digital-Recognization-Based-on-FPGA
  Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…
  ☆10Updated last year
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆23Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆68Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆39Updated 2 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆27Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆83Updated 4 years ago