yiwangchunyu / AI-RISC
Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
☆14Updated 3 years ago
Alternatives and similar repositories for AI-RISC:
Users that are interested in AI-RISC are comparing it to the libraries listed below
- ☆12Updated 5 years ago
- 3×3脉动阵列乘法器☆36Updated 5 years ago
- LSTM neural network (verilog)☆13Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- ☆16Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.☆48Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆34Updated 2 years ago
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- A scalable Eyeriss model in SystemC.☆24Updated 2 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆85Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- ☆14Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆22Updated 3 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆14Updated 2 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 weeks ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆93Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆22Updated 2 years ago
- ☆19Updated last year