Alternatives and similar repositories for AI-RISC

Users that are interested in AI-RISC are comparing it to the libraries listed below

• dldldlfma / eyeriss_v1
  ☆12Updated 5 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆53Updated 4 years ago
• zhehaoxu / ai-talk
  关于深度学习算法、框架、编译器、加速器的一些理解
  ☆16Updated 3 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆28Updated 2 years ago
• nitheeshkm / sigmoid_tanh_verilog
  Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project
  ☆16Updated 5 years ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆96Updated last year
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆105Updated 6 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆35Updated 5 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆47Updated 2 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆150Updated last year
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆24Updated 3 years ago
• dldldlfma / super_small_toy_tpu
  ☆41Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆53Updated 4 years ago
• ZhaoqxCN / PYNQ-CNN-ATTEMPT
  Some attempts to build CNN on PYNQ.
  ☆24Updated 6 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆113Updated 4 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆163Updated 5 years ago
• WenqiJiang / FPGA-Based-RNN-Accelerator-Using-Vivado-HLS
  This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …
  ☆23Updated 6 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆64Updated 6 months ago
• sefaburakokcu / finn-quantized-yolo
  Low-Precision YOLO on PYNQ with FINN
  ☆33Updated last year
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆103Updated 4 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆32Updated 5 years ago
• VGuoGavin / Hand-Writing-Digital-Recognization-Based-on-FPGA
  Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…
  ☆12Updated 2 years ago
• niexun / LSTM
  LSTM neural network (verilog)
  ☆15Updated 6 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆129Updated 4 months ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆49Updated 7 years ago
• MasLiang / CNN-On-FPGA
  FPGA
  ☆158Updated last year
• eldrickm / wakey_wakey
  EE 272B - VLSI Design Project
  ☆12Updated 4 years ago