IMPETUS-UdeS / rule4ml
Resource Utilization and Latency Estimation for ML on FPGA.
☆10Updated 2 months ago
Alternatives and similar repositories for rule4ml:
Users that are interested in rule4ml are comparing it to the libraries listed below
- High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs☆27Updated last month
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆30Updated last month
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- ☆71Updated 2 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆34Updated 2 weeks ago
- ☆23Updated 2 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- ☆92Updated 10 months ago
- ☆8Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆76Updated last week
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆51Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 weeks ago
- ☆11Updated 2 years ago
- ☆26Updated last month
- Generate versal system design from ONNX model. AI engine kernels. Sub-microsecond speeds for autoencoders.☆13Updated 4 months ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆24Updated last month
- Open-source of MSD framework☆16Updated last year
- ☆15Updated 10 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- An LSTM template and a few examples using Vivado HLS☆44Updated last year
- A heterogeneous accelerator-centric compute cluster☆15Updated last week
- Models and examples built with hls4ml☆12Updated 5 years ago
- Implementation of Microscaling data formats in SystemVerilog.☆18Updated 8 months ago
- ☆33Updated 6 years ago
- Fast inference of Boosted Decision Trees in FPGAs☆53Updated last month
- ☆29Updated 6 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago