pphilippos / simodense
Simodense: a RISC-V softcore for custom SIMD instructions
☆16Updated 6 months ago
Alternatives and similar repositories for simodense
Users that are interested in simodense are comparing it to the libraries listed below
Sorting:
- ☆61Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated last week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆57Updated 3 months ago
- Simple runtime for Pulp platforms☆47Updated 2 months ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated this week
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆100Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆108Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated last week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆16Updated last year
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 7 months ago
- ☆19Updated this week
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆151Updated this week
- Floating point modules for CHISEL☆32Updated 10 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆102Updated last year
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- ☆61Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆32Updated 6 months ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆34Updated last year
- PCI Express controller model☆56Updated 2 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago