pphilippos / simodenseLinks
Simodense: a RISC-V softcore for custom SIMD instructions
☆16Updated 3 months ago
Alternatives and similar repositories for simodense
Users that are interested in simodense are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- ☆73Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆163Updated 2 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆176Updated 2 weeks ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆108Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆177Updated last week
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- The multi-core cluster of a PULP system.☆108Updated this week
- ☆31Updated this week
- Floating point modules for CHISEL☆31Updated 10 years ago
- ☆54Updated last month
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆117Updated last week
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated 10 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆103Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆264Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆109Updated last week
- Chisel Learning Journey☆109Updated 2 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆105Updated 3 months ago
- Open-source high-performance non-blocking cache☆88Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- ☆107Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆83Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- A matrix extension proposal for AI applications under RISC-V architecture☆153Updated 6 months ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago