hsieh672 / SNN-AcceleratorView external linksLinks
A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The second layer is the hidden layer and has 100 neurons; the last layer is the output layer with 10 neurons.
☆15Sep 9, 2023Updated 2 years ago
Alternatives and similar repositories for SNN-Accelerator
Users that are interested in SNN-Accelerator are comparing it to the libraries listed below
Sorting:
- A Spiking Neuron Network Project in Verilog Implementation☆26Apr 5, 2018Updated 7 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 2 months ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆66Feb 18, 2024Updated last year
- ☆20Apr 7, 2021Updated 4 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆40Jun 29, 2020Updated 5 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Mar 30, 2023Updated 2 years ago
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆13Feb 16, 2024Updated last year
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆16Apr 12, 2024Updated last year
- Resource Utilization and Latency Estimation for ML on FPGA.☆18Feb 4, 2026Updated last week
- FPGA Design of a Spiking Neural Network.☆46May 15, 2024Updated last year
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆20Jun 17, 2020Updated 5 years ago
- ☆21Feb 5, 2026Updated last week
- An automated HDC platform☆11Jan 29, 2026Updated 2 weeks ago
- Offical implementation of High-Performance Temporal Reversible Spiking Neural Networks with $O(L)$ Training Memory and $O(1)$ Inference C…☆22Feb 3, 2026Updated last week
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆25Dec 10, 2019Updated 6 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆205Nov 4, 2023Updated 2 years ago
- Intelligent-Computing-Lab-Panda / Exploring-Temporal-Information-Dynamics-in-Spiking-Neural-NetworksPyTorch Implementation of Exploring Temporal Information Dynamics in Spiking Neural Networks (AAAI23)☆31Nov 25, 2022Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Sep 25, 2019Updated 6 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆33May 20, 2020Updated 5 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Vector Symbolic Architecture library☆11Mar 27, 2023Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Code and Results for Master Thesis Project on Fixed-point Quantization of Convolutional Neural Networks for Quantized Inference on Embedd…☆12Feb 7, 2021Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Fully opensource spiking neural network accelerator☆166Feb 13, 2023Updated 3 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Feb 18, 2022Updated 3 years ago
- ☆22Apr 28, 2025Updated 9 months ago
- This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 20…☆13Oct 20, 2020Updated 5 years ago
- Efficient single-pass hyperdimensional classifier. Mirror of https://gitlab.com/biaslab/onlinehd☆11Jan 31, 2021Updated 5 years ago
- SystemVerilog file list pruner☆16Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 10 months ago
- Hardware Description Language on FPGA☆10Sep 18, 2023Updated 2 years ago