hsieh672 / SNN-AcceleratorLinks
A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The second layer is the hidden layer and has 100 neurons; the last layer is the output layer with 10 neurons.
☆13Updated last year
Alternatives and similar repositories for SNN-Accelerator
Users that are interested in SNN-Accelerator are comparing it to the libraries listed below
Sorting:
- SNN on FPGA☆10Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- A repository FPGA-friendly SNN models☆34Updated 4 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆36Updated 4 years ago
- Spiking Neural Network RTL Implementation☆57Updated 4 years ago
- ☆19Updated 4 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 3 months ago
- A Spiking Neuron Network Project in Verilog Implementation☆23Updated 7 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆69Updated 2 weeks ago
- FPGA Design of a Spiking Neural Network.☆40Updated last year
- ☆25Updated 3 years ago
- Framework for radix encoded SNN on FPGA☆13Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆57Updated 3 years ago
- ☆17Updated 4 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆59Updated 2 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆16Updated 5 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 5 years ago
- ☆47Updated last year
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- I will share some useful or interesting papers about neuromorphic processor☆25Updated 4 months ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆84Updated 3 years ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆28Updated 9 months ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆185Updated 6 years ago
- ReRAM implementation on CNN☆18Updated 6 years ago