cceroici / Stochastic-Neural-Network

Related projects: ⓘ

• snagiri / CSE237D-PYNQ-SNN-Accelerator
  Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board
  ☆28Updated 5 years ago
• arkhodamoradi / s2n2
  ☆16Updated 3 years ago
• saunak1994 / CyNAPSEv11
  The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
  ☆30Updated 4 years ago
• zwhexplorer / Spiking-Neural-Network-Accelerator-EE552-project
  Spiking Neural Network Accelerator
  ☆12Updated 2 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆46Updated 3 years ago
• ChFrenkel / tinyODIN
  tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.
  ☆34Updated last year
• lirui-shanghaitech / A-convolution-kernel-implemented-by-Vivado-HLS
  This project implements a convolution kernel based on vivado HLS on zcu104
  ☆35Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• Angela-WangBo / Shenjing-RTL
  This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator
  ☆14Updated 4 years ago
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆9Updated 4 years ago
• eda-lab / CNNAF-CNN-Accelerator
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆9Updated 2 years ago
• vincent08tw / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆17Updated 3 years ago
• jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
  HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…
  ☆50Updated last year
• SFU-HiAccel / SyncNN
  [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
  ☆50Updated 3 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆58Updated 5 years ago
• jonathan93sh / CNNA
  A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA
  ☆20Updated 2 years ago
• puccinic / Transformer_dataflow
  C++ code for HLS FPGA implementation of transformer
  ☆12Updated last week
• adamsolomou / SC-DNN
  Stochastic Computing for Deep Neural Networks
  ☆28Updated 3 years ago
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆19Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆28Updated last month
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆23Updated 2 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆45Updated 2 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆21Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆38Updated 6 years ago
• oshears / SNN-FPGA-Implementation
  ☆12Updated 3 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆29Updated 3 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆35Updated 2 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆9Updated 3 years ago
• SivannaKing / SEU-ASIC-IOT-ECGAI
  Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators
  ☆13Updated last year
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆15Updated 5 months ago