Alternatives and similar repositories for column-combine

Users that are interested in column-combine are comparing it to the libraries listed below

• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• maestro-project / gamma
  ☆42Updated last year
• maestro-project / confuciux
  ☆32Updated 4 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 4 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• BradMcDanel / multiplication-free-dnn
  ☆10Updated 6 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆38Updated 5 years ago
• maeri-project / MAERI_bsv_isca2018
  MAERI public release
  ☆31Updated 4 years ago
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• hyoukjun / MAESTRO
  MAESTRO binary release
  ☆22Updated 6 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆20Updated 8 months ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 4 years ago
• hsharma35 / bitfusion
  Simulator for BitFusion
  ☆102Updated 5 years ago
• neurosim / DNN_NeuroSim_V1.1
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆22Updated 4 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 3 years ago
• isakedo / DNNsim
  ☆35Updated 5 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• maestro-project / magma
  ☆19Updated 3 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆47Updated 3 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 3 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆50Updated 11 months ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago