Alternatives and similar repositories for blog

Users that are interested in blog are comparing it to the libraries listed below

• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆52Updated 3 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• verilator / example-systemverilog
  ☆40Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆31Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 11 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆20Updated last year
• b224hisl / rioschip
  ☆33Updated 3 years ago
• open-design / riscv-soc-cores
  ☆41Updated 4 years ago
• pieter3d / simview
  ☆91Updated 3 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆70Updated last month
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆34Updated 4 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆92Updated 6 years ago