BUAA-CI-LAB / Literatures-on-SRAM-based-CIMLinks
A reading list for SRAM-based Compute-In-Memory (CIM) research.
☆65Updated 3 months ago
Alternatives and similar repositories for Literatures-on-SRAM-based-CIM
Users that are interested in Literatures-on-SRAM-based-CIM are comparing it to the libraries listed below
Sorting:
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆68Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month
- An integrated CGRA design framework☆89Updated 2 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆51Updated last year
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ☆111Updated 4 years ago
- 关于移植模型至gemmini的文档☆27Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 10 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆68Updated last year
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆135Updated 2 years ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 11 months ago
- ☆65Updated 3 months ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆16Updated 2 months ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆80Updated last month
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆53Updated 2 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆150Updated 2 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆64Updated 2 years ago