horizon-research / imagen
☆8Updated 2 months ago
Alternatives and similar repositories for imagen:
Users that are interested in imagen are comparing it to the libraries listed below
- ☆25Updated 3 years ago
- ☆33Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆16Updated 2 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆18Updated 9 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆30Updated 11 months ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆14Updated 3 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- ☆33Updated 4 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- A co-design architecture on sparse attention☆52Updated 3 years ago
- ☆39Updated 10 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆28Updated 2 years ago
- Heterogenous ML accelerator☆18Updated 7 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆51Updated last month
- DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators☆14Updated 6 months ago
- ☆10Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 weeks ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 3 weeks ago
- ☆29Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆38Updated 2 years ago
- ☆29Updated 4 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆15Updated 10 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated last month
- [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS☆12Updated 3 months ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆36Updated 2 years ago
- Artifact for paper "PIM is All You Need: A CXL-Enabled GPU-Free System for LLM Inference", ASPLOS 2025☆52Updated last week