neurosim / NeuroSim
Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected here and not in the old repositories.
☆33Updated 2 weeks ago
Alternatives and similar repositories for NeuroSim:
Users that are interested in NeuroSim are comparing it to the libraries listed below
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆82Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆61Updated 2 weeks ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆47Updated 3 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆55Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆67Updated last year
- ☆18Updated 2 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- ☆53Updated 2 weeks ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆64Updated 2 years ago
- ☆25Updated 11 months ago
- ☆15Updated 10 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆42Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated last month
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- ☆16Updated last month
- ☆33Updated this week
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆14Updated 5 years ago
- Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.☆44Updated last year
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆38Updated 5 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆159Updated last year
- Fully opensource spiking neural network accelerator☆138Updated 2 years ago
- ☆45Updated last year
- Spiking Neural Network Accelerator☆15Updated 2 years ago
- A reading list for SRAM-based Compute-In-Memory (CIM) research.☆54Updated last month
- ☆16Updated 3 years ago
- ☆17Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago