neurosim / DNN_NeuroSim_V1.4
Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
☆53Updated 6 months ago
Related projects ⓘ
Alternatives and complementary repositories for DNN_NeuroSim_V1.4
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆118Updated 8 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆45Updated 3 years ago
- A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems☆141Updated 5 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆64Updated 10 months ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆21Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆31Updated 2 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆22Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆41Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆34Updated 5 years ago
- ☆45Updated 2 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 3 years ago
- Benchmark framework of synaptic device technologies for a simple neural network☆181Updated 3 years ago
- [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…☆55Updated last year
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆19Updated 11 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆110Updated last year
- ☆33Updated 4 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆21Updated 5 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆28Updated last month
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆26Updated 3 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆128Updated 4 years ago
- MICRO22 artifact evaluation for Sparseloop☆38Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆66Updated 3 months ago
- eyeriss-chisel3☆38Updated 2 years ago
- ☆24Updated 7 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆113Updated this week
- Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).☆15Updated 3 years ago
- HW accelerator mapping optimization framework for in-memory computing☆18Updated 2 months ago