CMU-SAFARI / MIMDRAM
Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing''. Paper is at: https://arxiv.org/pdf/2402.19080.pdf
☆16Updated this week
Alternatives and similar repositories for MIMDRAM:
Users that are interested in MIMDRAM are comparing it to the libraries listed below
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- ☆21Updated 2 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆27Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆55Updated 3 months ago
- gem5 repository to study chiplet-based systems☆69Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Processing in Memory Emulation☆18Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆60Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆57Updated 6 months ago
- CGRA framework with vectorization support.☆21Updated this week
- ☆40Updated 10 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆39Updated 8 months ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆77Updated last year
- ☆23Updated 3 months ago
- ☆52Updated 11 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆66Updated 5 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆84Updated 3 months ago
- ☆9Updated last year
- ☆23Updated 4 years ago
- Dataset for ML-guided Accelerator Design☆33Updated 2 months ago
- HW accelerator mapping optimization framework for in-memory computing☆21Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆58Updated last week
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated 10 months ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆15Updated 5 years ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆16Updated 2 years ago
- ☆17Updated last year