IBM / 3D-CiM-LLM-Inference-SimulatorLinks
Simulator for LLM inference on an abstract 3D AIMC-based accelerator
☆22Updated 3 months ago
Alternatives and similar repositories for 3D-CiM-LLM-Inference-Simulator
Users that are interested in 3D-CiM-LLM-Inference-Simulator are comparing it to the libraries listed below
Sorting:
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- ☆64Updated last month
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago
- Open-source of MSD framework☆16Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆100Updated 11 months ago
- ☆35Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- ☆49Updated 3 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆112Updated 2 years ago
- ☆28Updated 4 months ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆124Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- Collection of kernel accelerators optimised for LLM execution☆19Updated 4 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆83Updated 6 months ago
- ☆47Updated 3 weeks ago
- ☆54Updated last year
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆30Updated 2 weeks ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆34Updated 6 months ago
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆42Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆68Updated 5 months ago
- ☆18Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆123Updated 5 months ago
- Implementation of Microscaling data formats in SystemVerilog.☆23Updated last month
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆135Updated 5 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago