Alternatives and similar repositories for SRAM-Compute-In-Memory

Users that are interested in SRAM-Compute-In-Memory are comparing it to the libraries listed below

• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆94Updated 3 weeks ago
• neurosim / DNN_NeuroSim_V1.4
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆76Updated 8 months ago
• skycrapers / AM-Lib
  ☆29Updated 2 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆92Updated 3 years ago
• neurosim / DNN_NeuroSim_V1.3
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆74Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆138Updated 6 months ago
• sunxt99 / PIMCOMP-NN
  ☆71Updated 9 months ago
• thu-nics / MNSIM-2.0
  A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems
  ☆186Updated 11 months ago
• adervay1 / CIMulator
  a Computing In Memory emULATOR framework
  ☆14Updated last year
• wangxy-2000 / pimsim-nn
  ☆58Updated last year
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆70Updated 2 weeks ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆91Updated last year
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆120Updated 5 years ago
• neurosim / DNN_NeuroSim_V2.0
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆53Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆176Updated 5 years ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆159Updated this week
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆58Updated 3 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆35Updated 3 years ago
• ECASLab / hls-fpga-accelerators
  Collection of kernel accelerators optimised for LLM execution
  ☆24Updated last month
• RakeshUIUC / multihead_attn_accelerator
  Accelerate multihead attention transformer model using HLS for FPGA
  ☆12Updated last year
• booniebears / CoMN
  ☆18Updated last year
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆44Updated 4 months ago
• neurosim / DNN_NeuroSim_V2.1
  Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
  ☆172Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 8 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆30Updated 2 years ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆137Updated 9 months ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆75Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆82Updated 4 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago