char-fish-after-lunch / SystemOnCatView external linksLinks
An SoC with multiple RISC-V IMA processors.
☆19Aug 1, 2018Updated 7 years ago
Alternatives and similar repositories for SystemOnCat
Users that are interested in SystemOnCat are comparing it to the libraries listed below
Sorting:
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 2 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 5 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 weeks ago
- A naive verilog/systemverilog formatter☆21Mar 22, 2025Updated 10 months ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Compiling finite generators to digital logic. WIP☆13Aug 24, 2020Updated 5 years ago
- Operating System Simulator☆18Jun 18, 2019Updated 6 years ago
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- Test cases for MIPS CPU implementation☆12Dec 26, 2019Updated 6 years ago
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆14Jun 29, 2020Updated 5 years ago
- Documentation for Router Lab☆70Nov 19, 2025Updated 2 months ago
- Porting mgba emulator to kendryte K210.☆30Apr 7, 2019Updated 6 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 6 years ago
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 5 months ago
- An advanced cross-platform serial port utility☆26Dec 28, 2025Updated last month
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 3 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Dec 1, 2019Updated 6 years ago
- Implementation of several grid routers in Rust☆13Oct 21, 2025Updated 3 months ago
- 开源软件供应链点亮计划 - 暑期2020的主页代码。This repository is the homepage for Open Source Promotion Plan - Summer 2020 built with create-react-app.☆10Aug 28, 2024Updated last year
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Binary translation in Rust☆13Jun 22, 2020Updated 5 years ago
- nscscc2018☆27Oct 11, 2018Updated 7 years ago
- Documentation for TCP Lab☆12May 20, 2025Updated 8 months ago
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.☆49Mar 29, 2022Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 2 months ago
- THU compiler principle course homework, written in rust. (this is not the pa framework)☆13Dec 24, 2018Updated 7 years ago
- Labs for Network Principle course, Fall 2018, Tsinghua University☆18Jun 6, 2019Updated 6 years ago
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Oct 8, 2021Updated 4 years ago
- 计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位☆127Dec 4, 2025Updated 2 months ago
- hacktastic stlink swo/swv magical plaything (maybe)☆20Dec 19, 2014Updated 11 years ago
- Communicate undetected in plain sight using zero width obfuscation.☆15Nov 5, 2021Updated 4 years ago
- ☆18Jul 9, 2025Updated 7 months ago
- 根据进程pid，利用ptrace从内存中重建ELF可执行文件☆16May 17, 2019Updated 6 years ago
- Microarchitecture diagrams of several CPUs☆47Feb 7, 2026Updated last week