char-fish-after-lunch / SystemOnCatLinks
An SoC with multiple RISC-V IMA processors.
☆19Updated 7 years ago
Alternatives and similar repositories for SystemOnCat
Users that are interested in SystemOnCat are comparing it to the libraries listed below
Sorting:
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated 9 months ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- RV32I by cats☆16Updated 2 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆44Updated last year
- A naive verilog/systemverilog formatter☆21Updated 5 months ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 2 years ago
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- A hand-written recursive decent Verilog parser.☆11Updated 3 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- chipyard in mill :P☆78Updated last year
- Baremetal softwares for TrivialMIPS platform☆11Updated 6 years ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 6 months ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆107Updated 6 years ago
- My knowledge base☆66Updated this week
- RISC-V architecture concurrency model litmus tests☆89Updated 3 months ago
- A prototype GUI for chisel-development☆52Updated 5 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- ☆36Updated last week
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Updated 6 years ago
- uCore OS Labs on Berkeley bootloader☆39Updated 7 years ago
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆11Updated 6 years ago
- Microarchitecture diagrams of several CPUs☆42Updated last week
- What if everything is a io_uring?☆16Updated 2 years ago