char-fish-after-lunch / SystemOnCatLinks
An SoC with multiple RISC-V IMA processors.
☆19Updated 7 years ago
Alternatives and similar repositories for SystemOnCat
Users that are interested in SystemOnCat are comparing it to the libraries listed below
Sorting:
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated 10 months ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- RV32I by cats☆15Updated 2 years ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 4 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 2 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 7 months ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Updated 6 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A bare-metal application to test specific features of the risc-v hypervisor extension☆42Updated last year
- A naive verilog/systemverilog formatter☆21Updated 6 months ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆108Updated 6 years ago
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Microarchitecture diagrams of several CPUs☆43Updated 3 weeks ago
- Baremetal softwares for TrivialMIPS platform☆11Updated 6 years ago
- A prototype GUI for chisel-development☆51Updated 5 years ago
- My knowledge base☆67Updated last week
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated last month
- Synthesisable SIMT-style RISC-V GPGPU☆41Updated 3 months ago
- The 'missing header' for Chisel☆21Updated 6 months ago
- chipyard in mill :P☆77Updated last year
- nscscc2018☆26Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- ☆167Updated 4 years ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Updated last year