akshaymdas / OpenLANE-SkyWater130-workshopLinks
This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK.
☆22Updated 4 years ago
Alternatives and similar repositories for OpenLANE-SkyWater130-workshop
Users that are interested in OpenLANE-SkyWater130-workshop are comparing it to the libraries listed below
Sorting:
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆73Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆54Updated 4 years ago
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆47Updated 5 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆66Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆101Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- Static Timing Analysis Full Course☆63Updated 3 years ago
- Home of the open-source EDA course.☆52Updated 7 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- Design Verification Engineer interview preparation guide.☆43Updated 6 months ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆23Updated 3 years ago
- ☆47Updated last year
- ☆14Updated 2 years ago
- SystemVerilog RTL Linter for YoSys☆23Updated last year
- ☆17Updated 2 years ago
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆48Updated last week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆68Updated 2 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆158Updated 3 weeks ago
- ☆40Updated 7 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- Structured UVM Course☆58Updated 2 years ago
- An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders☆22Updated 3 weeks ago