☆19Oct 20, 2025Updated 5 months ago
Alternatives and similar repositories for 100RTL
Users that are interested in 100RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Shielded Enclaves for Cloud FPGAs☆15Nov 24, 2021Updated 4 years ago
- ☆12Aug 19, 2020Updated 5 years ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆14Nov 13, 2024Updated last year
- Custom 64-bit pipelined RISC processor☆18Dec 8, 2025Updated 4 months ago
- Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs☆14Apr 1, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆34Jan 18, 2025Updated last year
- Example SystemVerilog UVM Environment☆10Jun 23, 2015Updated 10 years ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- ☆16Apr 8, 2023Updated 3 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Open Source VLSI Tools☆29Feb 6, 2021Updated 5 years ago
- PSA-ADAC SDC-600 Secure Debug Manager library for authenticated debug☆15Mar 18, 2025Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆16Aug 13, 2023Updated 2 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- ☆13Aug 3, 2021Updated 4 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- An 8-Bit CPU implemented in an FPGA☆21Jun 8, 2020Updated 5 years ago
- A Post-Quantum Encryption Algorithm☆17Jul 3, 2020Updated 5 years ago
- An implementation of the NTRU encryption and decryption algorithm in Python 3☆16Sep 29, 2024Updated last year
- ☆18Jun 12, 2023Updated 2 years ago
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆17Jun 11, 2025Updated 10 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- HackerRank test solutions for FPGA engineer interview at Optiver☆16Jun 7, 2020Updated 5 years ago
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆28Aug 15, 2025Updated 7 months ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- Vehicle templates with multibody suspension and electric powertrain sized for Formula Student competitions.☆16Feb 25, 2026Updated last month
- Modern CV template for Typst☆12Mar 30, 2026Updated last week
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Jul 12, 2023Updated 2 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year
- ☆16May 23, 2024Updated last year
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆33Nov 25, 2024Updated last year
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆21Jul 21, 2025Updated 8 months ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 8 months ago
- ☆14Apr 29, 2024Updated last year
- Examples for compiling code using the RISC-V gnu toolchain☆21Jan 3, 2026Updated 3 months ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 8 months ago