TinyTapeout / siliwiz
Silicon Layout Wizard
☆148Updated this week
Related projects: ⓘ
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆104Updated this week
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆138Updated 3 months ago
- Simulate electronic circuit using Python and the Ngspice / Xyce simulators☆146Updated last year
- A configurable RTL to bitstream FPGA toolchain☆253Updated last week
- Example LED blinking project for your FPGA dev board of choice☆162Updated 3 weeks ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆169Updated last year
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆39Updated 4 months ago
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆89Updated last month
- A modern schematic entry and simulation program☆67Updated 8 months ago
- Book repository "Analysis and Design of Elementary MOS Amplifier Stages"☆327Updated 3 weeks ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆312Updated this week
- TinyTapeout-02 submission repository☆26Updated 5 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆154Updated 6 months ago
- Documenting Lattice's 28nm FPGA parts☆143Updated 8 months ago
- List of FPGA Lattice boards using open tools☆303Updated 5 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆70Updated 2 weeks ago
- Converts GDSII files to STL files.☆35Updated 9 months ago
- Example designs showing different ways to use F4PGA toolchains.☆263Updated 5 months ago
- Board definitions for Amaranth HDL☆105Updated last month
- ADMS is a code generator for the Verilog-AMS language☆91Updated last year
- Graded exercises for nMigen (WIP)☆55Updated 3 years ago
- 130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design☆372Updated this week
- A work-in-progress board-level hardware description language (HDL) providing design automation through generators and block polymorphism.☆70Updated this week
- iCEBreaker Workshop☆119Updated 7 months ago
- VHDL to Discrete Logic on PCB Flow☆111Updated 10 months ago
- Synthesizable temperature sensor for Tiny Tapeout 03, developed by IIC@JKU.☆20Updated 8 months ago
- VHDL library 4 FPGAs☆167Updated this week
- Submission template for Tiny Tapeout 03☆19Updated last year
- ☆278Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆107Updated 11 months ago