asinghani / crypto-accelerator-chipLinks
Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December 2020.
☆23Updated 4 years ago
Alternatives and similar repositories for crypto-accelerator-chip
Users that are interested in crypto-accelerator-chip are comparing it to the libraries listed below
Sorting:
- ☆33Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- SRAM Design using OpenSource Applications☆23Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Various examples for Chisel HDL☆30Updated 3 years ago
- ☆38Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆35Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- ☆88Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- A configurable SRAM generator☆56Updated 3 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Demo SoC for SiliconCompiler.☆62Updated 3 weeks ago
- Naive Educational RISC V processor☆92Updated 2 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- The RTL source for AnyCore RISC-V☆33Updated 3 years ago
- SpinalHDL - Cryptography libraries☆57Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- sram/rram/mram.. compiler☆43Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆20Updated 8 months ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 10 months ago
- An automatic clock gating utility☆51Updated 8 months ago