Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December 2020.
☆26Jan 13, 2021Updated 5 years ago
Alternatives and similar repositories for crypto-accelerator-chip
Users that are interested in crypto-accelerator-chip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Cryptography accelerator core (for AES128/AES256 and SHA256) designed in Chisel3, primarily targeting ASIC platforms.☆11Jan 11, 2021Updated 5 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (build-environment repo).☆11Jan 13, 2021Updated 5 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Jul 22, 2021Updated 5 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆16Dec 19, 2017Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆14Oct 22, 2023Updated 3 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 5 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆20Jan 28, 2022Updated 4 years ago
- This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface.…☆22Oct 28, 2024Updated 2 years ago
- ☆17Aug 7, 2026Updated 2 months ago
- RISC-V AI Accelerator SoC with innovative BitNet multiplier-free architecture. Features PicoRV32 CPU, dual AI accelerators (6.4 GOPS), an…☆13Jan 20, 2026Updated 9 months ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆17Aug 30, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- ☆59Sep 30, 2023Updated 3 years ago
- ROS package for generating motion-profiled spline path trajectories using Pathfinder☆10Feb 21, 2020Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated last year
- The MINA Instruction Set Architecture.☆17Apr 7, 2023Updated 3 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆23Jul 5, 2021Updated 5 years ago
- Collection of different communication methods for chip mulitprocessors☆13Jul 20, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- The BT656_out module is a configurable BT.656 video encoder that supports both 8-bit and 10-bit video output formats. This implementation…☆16Jan 6, 2026Updated 9 months ago
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 8 months ago
- An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.☆13Jan 4, 2026Updated 9 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆138Feb 22, 2022Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Aug 28, 2025Updated last year
- Field cleaner for models in Ruby on Rails. Strips extra spaces among other things.☆13Mar 2, 2026Updated 7 months ago
- Dual-issue RV64IM processor for fun & learning☆65Jul 4, 2023Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆31Jan 10, 2024Updated 2 years ago
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Configurable AES-GCM IP (128, 192, 256 bits)☆44Aug 10, 2026Updated 2 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆77Mar 16, 2026Updated 7 months ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆32Mar 9, 2021Updated 5 years ago
- Basic scripts for Synopsys Design Compiler and Synopsys IC Compiler☆10Mar 31, 2018Updated 8 years ago
- The 64 bit OpenPOWER Microwatt core, MPW1 tape out☆16Oct 29, 2021Updated 5 years ago
- FPGA core for SHA256d mining targeting Lattice iCE40 devices.☆22Jun 13, 2021Updated 5 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago