hzeller / gds2vecLinks
A simple program to convert gdsII files to vector output formats. Currently used to create laser-cut models of standard cells.
☆12Updated 2 years ago
Alternatives and similar repositories for gds2vec
Users that are interested in gds2vec are comparing it to the libraries listed below
Sorting:
- The specification for the FIRRTL language☆63Updated last week
- C++ library to create and read GDSII file☆22Updated last year
- ☆15Updated last year
- ☆14Updated 9 years ago
- Framework Open EDA Gui☆68Updated 9 months ago
- ☆18Updated 2 years ago
- FPGA Assembly (FASM) Parser and Generator☆97Updated 3 years ago
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆57Updated 5 years ago
- A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integra…☆39Updated 9 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Visual Simulation of Register Transfer Logic☆101Updated last month
- Benchmarks for Yosys development☆24Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆81Updated 3 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated this week
- Quite OK image compression Verilog implementation☆22Updated 9 months ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆34Updated 2 months ago
- Library of FPGA architectures☆24Updated last week
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆12Updated last year
- FPGA tool performance profiling☆102Updated last year
- Prefix tree adder space exploration library☆57Updated 10 months ago
- Generate bitstream from FPGA assembly.☆23Updated 2 months ago
- Web-based HDL diagramming tool☆79Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 months ago
- Demo SoC for SiliconCompiler.☆61Updated this week
- Extensible FPGA control platform☆61Updated 2 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆54Updated 4 months ago
- Simulation VCD waveform viewer, using old Motif UI☆27Updated 2 years ago