foshardware / lsc
Libre Silicon Compiler
☆23Updated 3 years ago
Alternatives and similar repositories for lsc:
Users that are interested in lsc are comparing it to the libraries listed below
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- The PE for the second generation CGRA (garnet).☆17Updated last week
- Logic circuit analysis and optimization☆36Updated 5 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- ☆18Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Equivalence checking with Yosys☆40Updated 2 weeks ago
- Coriolis VLSI EDA Tool (LIP6)☆62Updated last month
- ☆55Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- An automatic clock gating utility☆45Updated 8 months ago
- ☆33Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Fluid Pipelines☆11Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆20Updated 2 years ago
- ☆22Updated last year
- Mutation Cover with Yosys (MCY)☆80Updated 2 weeks ago
- RISC-V BSV Specification☆19Updated 5 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆25Updated 4 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- netlistDB - Intermediate format for digital hardware representation with graph database API☆30Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Useful utilities for BAR projects☆31Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆28Updated this week