foshardware / lsc
Libre Silicon Compiler
☆23Updated 4 years ago
Alternatives and similar repositories for lsc:
Users that are interested in lsc are comparing it to the libraries listed below
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- The PE for the second generation CGRA (garnet).☆17Updated 2 weeks ago
- RISC-V BSV Specification☆20Updated 5 years ago
- BTOR2 MLIR project☆25Updated last year
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 3 months ago
- Equivalence checking with Yosys☆42Updated last week
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last week
- ☆55Updated 2 years ago
- An advanced header-only exact synthesis library☆25Updated 2 years ago
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- A fault-injection framework using Chisel and FIRRTL☆35Updated 2 years ago
- Logic circuit analysis and optimization☆35Updated 5 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 4 years ago
- Bitstream Fault Analysis Tool☆13Updated last year
- ☆13Updated 4 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated last month
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- ☆18Updated 4 years ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆13Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- Integer Multiplier Generator for Verilog☆22Updated last year