Open SoC Debug Hardware Reference Implementation
☆16Jul 15, 2019Updated 6 years ago
Alternatives and similar repositories for osd-hw
Users that are interested in osd-hw are comparing it to the libraries listed below
Sorting:
- ☆10Jun 30, 2021Updated 4 years ago
- ☆17Jun 24, 2021Updated 4 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Miscellaneous components for bluespec☆11Nov 18, 2024Updated last year
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 6 years ago
- Android AOA2.0(ADK2) for Arduino☆13Sep 12, 2012Updated 13 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- DEPRECATED: Use ghc-heap, ghc-heap-view in GHC 8.x instead.☆18Sep 17, 2016Updated 9 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Feb 16, 2022Updated 4 years ago
- ☆10Mar 18, 2020Updated 6 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- A nix expression to create a netboot k8s cluster of qemu instances.☆16May 21, 2018Updated 7 years ago
- ☆88Updated this week
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Jul 11, 2018Updated 7 years ago
- A VHDL implementation of SipHash☆13Feb 19, 2015Updated 11 years ago
- Rust types for the debug server protocol☆11Jul 7, 2019Updated 6 years ago
- I ❤︎ FEM: A finite element method demo in Umka and tophat☆18Jul 12, 2025Updated 8 months ago
- Regex Engine using SIMD and Roaring-Bitmaps☆11Dec 26, 2022Updated 3 years ago
- Verilator open-source SystemVerilog simulator and lint system☆42Updated this week
- A game development framework that provides basic tooling and a content authoring workflow☆58Nov 7, 2020Updated 5 years ago
- This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.☆12Aug 19, 2018Updated 7 years ago
- ☆12Jul 17, 2020Updated 5 years ago
- Linux Kernel☆14Oct 27, 2017Updated 8 years ago
- Simple Game Engine Focusing on Vulkan Ray Tracing☆57Nov 15, 2021Updated 4 years ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Mar 9, 2026Updated last week
- Description of a RISC-V architecture based on MIPS 3000☆13Apr 24, 2023Updated 2 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- coursera code☆13Jun 27, 2013Updated 12 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 13 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- Language for simplifying parameterized RTL design☆13Nov 6, 2024Updated last year
- ☆14Sep 25, 2013Updated 12 years ago
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago