masc-ucsc / esesc
ESESC: A Fast Multicore Simulator
☆134Updated 3 years ago
Alternatives and similar repositories for esesc:
Users that are interested in esesc are comparing it to the libraries listed below
- A wrapper for the SPEC CPU2006 benchmark suite.☆86Updated 3 years ago
- Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator☆72Updated 8 months ago
- DRAMSim2: A cycle accurate DRAM simulator☆260Updated 4 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆130Updated last year
- ☆30Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆146Updated 2 years ago
- Official repository of the Arm Research Starter Kit on System Modeling using gem5☆113Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆176Updated 4 years ago
- RISC-V Torture Test☆175Updated 6 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆153Updated 4 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- Creating beautiful gem5 simulations☆47Updated 3 years ago
- The Splash-3 benchmark suite☆42Updated last year
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆78Updated last month
- A fast and scalable x86-64 multicore simulator☆342Updated last year
- gem5 Tips & Tricks☆65Updated 4 years ago
- ☆88Updated 11 months ago
- Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.☆178Updated 2 years ago
- Extremely Simple Microbenchmarks☆30Updated 6 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆163Updated 5 months ago
- A heterogeneous architecture timing model simulator.☆144Updated last month
- Connectal is a framework for software-driven hardware development.☆163Updated last year
- Comment on the rocket-chip source code☆169Updated 6 years ago
- The Sniper Multi-Core Simulator☆108Updated 2 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆138Updated last month
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆98Updated 5 years ago
- The OpenPiton Platform☆28Updated last year
- Memory System Microbenchmarks☆62Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 6 months ago
- RiVEC Bencmark Suite☆108Updated last month